fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
This commit is contained in:
Sebastien Bourdeauducq
parent
55d143a454
commit
261166d92b
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@ -20,14 +20,14 @@ def _printsig(ns, s):
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def _printintbool(node):
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if isinstance(node, bool):
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if node:
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return "1'd1"
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return "1'd1", False
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else:
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return "1'd0"
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return "1'd0", False
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elif isinstance(node, int):
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if node >= 0:
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return str(bits_for(node)) + "'d" + str(node)
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return str(bits_for(node)) + "'d" + str(node), False
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else:
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return "-" + str(bits_for(node)) + "'sd" + str(-node)
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return "-" + str(bits_for(node)) + "'sd" + str(-node), True
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else:
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raise TypeError
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@ -35,16 +35,32 @@ def _printexpr(ns, node):
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if isinstance(node, (int, bool)):
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return _printintbool(node)
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elif isinstance(node, Signal):
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return ns.get_name(node)
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return ns.get_name(node), node.signed
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elif isinstance(node, _Operator):
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arity = len(node.operands)
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r1, s1 = _printexpr(ns, node.operands[0])
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if arity == 1:
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r = node.op + _printexpr(ns, node.operands[0])
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if node.op == "-":
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if s1:
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r = node.op + r1
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else:
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r = "-$signed({1'd0, " + r1 + "})"
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s = True
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else:
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r = node.op + r1
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s = s1
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elif arity == 2:
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r = _printexpr(ns, node.operands[0]) + " " + node.op + " " + _printexpr(ns, node.operands[1])
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r2, s2 = _printexpr(ns, node.operands[1])
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if node.op in ["+", "-", "*", "&", "^", "|"]:
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if s2 and not s1:
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r1 = "$signed({1'd0, " + r1 + "})"
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if s1 and not s2:
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r2 = "$signed({1'd0, " + r2 + "})"
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r = r1 + " " + node.op + " " + r2
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s = s1 or s2
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else:
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raise TypeError
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return "(" + r + ")"
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return "(" + r + ")", s
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elif isinstance(node, _Slice):
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# Verilog does not like us slicing non-array signals...
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if isinstance(node.value, Signal) \
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@ -56,13 +72,13 @@ def _printexpr(ns, node):
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sr = "[" + str(node.start) + "]"
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else:
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sr = "[" + str(node.stop-1) + ":" + str(node.start) + "]"
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return _printexpr(ns, node.value) + sr
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r, s = _printexpr(ns, node.value)
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return r + sr, s
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elif isinstance(node, Cat):
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l = list(map(partial(_printexpr, ns), node.l))
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l.reverse()
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return "{" + ", ".join(l) + "}"
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l = [_printexpr(ns, v)[0] for v in reversed(node.l)]
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return "{" + ", ".join(l) + "}", False
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elif isinstance(node, Replicate):
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return "{" + str(node.n) + "{" + _printexpr(ns, node.v) + "}}"
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return "{" + str(node.n) + "{" + _printexpr(ns, node.v) + "}}", False
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else:
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raise TypeError
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@ -80,11 +96,11 @@ def _printnode(ns, at, level, node):
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assignment = " = "
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else:
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assignment = " <= "
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return "\t"*level + _printexpr(ns, node.l) + assignment + _printexpr(ns, node.r) + ";\n"
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return "\t"*level + _printexpr(ns, node.l)[0] + assignment + _printexpr(ns, node.r)[0] + ";\n"
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elif isinstance(node, list):
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return "".join(list(map(partial(_printnode, ns, at, level), node)))
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elif isinstance(node, If):
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r = "\t"*level + "if (" + _printexpr(ns, node.cond) + ") begin\n"
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r = "\t"*level + "if (" + _printexpr(ns, node.cond)[0] + ") begin\n"
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r += _printnode(ns, at, level + 1, node.t)
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if node.f:
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r += "\t"*level + "end else begin\n"
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@ -93,10 +109,10 @@ def _printnode(ns, at, level, node):
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return r
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elif isinstance(node, Case):
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if node.cases:
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r = "\t"*level + "case (" + _printexpr(ns, node.test) + ")\n"
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r = "\t"*level + "case (" + _printexpr(ns, node.test)[0] + ")\n"
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css = sorted([(k, v) for (k, v) in node.cases.items() if k != "default"], key=itemgetter(0))
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for choice, statements in css:
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r += "\t"*(level + 1) + _printexpr(ns, choice) + ": begin\n"
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r += "\t"*(level + 1) + _printexpr(ns, choice)[0] + ": begin\n"
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r += _printnode(ns, at, level + 2, statements)
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r += "\t"*(level + 1) + "end\n"
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if "default" in node.cases:
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@ -176,7 +192,7 @@ def _printcomb(f, ns, display_run):
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if display_run:
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r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
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for t in g[0]:
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r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset) + ";\n"
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r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
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r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
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r += syn_off
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r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
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@ -223,7 +239,7 @@ def _printinstances(f, ns, clock_domains):
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for p in x.items:
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if isinstance(p, Instance._IO):
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name_inst = p.name
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name_design = _printexpr(ns, p.expr)
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name_design = _printexpr(ns, p.expr)[0]
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elif isinstance(p, Instance.ClockPort):
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name_inst = p.name_inst
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name_design = ns.get_name(clock_domains[p.domain].clk)
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@ -259,7 +275,7 @@ def _printinit(f, ios, ns):
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if signals:
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r += "initial begin\n"
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for s in sorted(signals, key=lambda x: x.huid):
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r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset) + ";\n"
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r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
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r += "end\n\n"
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return r
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