add hack to generate verilog with AsyncResetSynchronizer (FIXME)

litescope/frontend/la.py

@@ -1,4 +1,6 @@
 from migen.fhdl.std import *
+from migen.fhdl.specials import Special
+from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.fhdl import verilog
 from migen.bank.description import *
 from migen.actorlib.fifo import AsyncFIFO
@@ -84,7 +86,25 @@ class LiteScopeLA(Module, AutoCSR):
 			self.comb += sink.connect(recorder.dat_sink)
 
 	def export(self, design, layout, filename):
-		ret, ns = verilog.convert(design, return_ns=True)
+		# XXX FIXME
+		class SimAsyncResetSynchronizer(Special):
+			def __init__(self, cd, async_reset):
+				Special.__init__(self)
+				self.cd = cd
+				self.async_reset = async_reset
+
+			def iter_expressions(self):
+				yield self.cd, "clk", SPECIAL_INPUT
+				yield self.cd, "rst", SPECIAL_OUTPUT
+				yield self, "async_reset", SPECIAL_INPUT
+
+			@staticmethod
+			def lower(dr):
+				return Module()
+		so = {
+			AsyncResetSynchronizer:	SimAsyncResetSynchronizer
+		}
+		ret, ns = verilog.convert(design, return_ns=True, special_overrides=so)
 		r = ""
 		def format_line(*args):
 			return ",".join(args) + "\n"

make.py

@@ -21,7 +21,7 @@ def _get_args():
 		description="""\
 LiteScope - based on Migen.
 
-This program builds and/or loads LiteSATA components.
+This program builds and/or loads LiteScope components.
 One or several actions can be specified:
 
 clean           delete previous build(s).