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platforms/kc705: fix .bin generation with ISE and Vivado

This commit is contained in:
Florent Kermarrec 2015-03-29 12:16:33 +02:00 committed by Sebastien Bourdeauducq
parent 72fae61525
commit 263fc47728
1 changed files with 5 additions and 1 deletions
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6
mibuild/platforms/kc705.py
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@ -383,7 +383,11 @@ class Platform(XilinxPlatform):
def __init__(self, toolchain="vivado", programmer="xc3sprog"):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors,
toolchain=toolchain)
self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
if toolchain == "ise":
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
elif toolchain == "vivado":
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
def create_programmer(self):