Fix syntax errors and other stupid problems

migen/bus/asmibus.py

@@ -25,7 +25,7 @@ class Slot:
 		comb = []
 		sync = [
 			If(self.allocate,
-				self.state.eq(SLOT_PENDING)
+				self.state.eq(SLOT_PENDING),
 				self.we.eq(self.allocate_we),
 				self.adr.eq(self.allocate_adr)
 			),
@@ -39,7 +39,7 @@ class Slot:
 			sync += [
 				If(self.allocate,
 					self._counter.eq(self.time)
-				).Elif(self._counter.eq != 0,
+				).Elif(self._counter != 0,
 					self._counter.eq(self._counter - 1)
 				)
 			]
@@ -68,6 +68,7 @@ class Port:
 	def finalize(self, tagbits, base):
 		if self.finalized:
 			raise FinalizeError
+		self.finalized = True
 		self.tagbits = tagbits
 		self.base = base
 		nslots = len(self.slots)
@@ -121,7 +122,9 @@ class Hub:
 	def get_port(self, nslots=1):
 		if self.finalized:
 			raise FinalizeError
-		self.ports.append(Port(self, nslots))
+		new_port = Port(self, nslots)
+		self.ports.append(new_port)
+		return new_port
 	
 	def finalize(self):
 		if self.finalized:

migen/bus/wishbone2asmi.py

@@ -60,9 +60,9 @@ class WB2ASMI:
 				data_di.eq(self.asmiport.dat_r),
 				data_we.eq(Replicate(1, adw//8))
 			).Else(
-				data_di.eq(Replicate(self.wishbone.dat_i, adw//32),
+				data_di.eq(Replicate(self.wishbone.dat_i, adw//32)),
 				If(self.wishbone.cyc_i & self.wishbone.stb_i & self.wishbone.ack_o,
-					displacer(self.wishbone.we_i, adr_offset, data_we)
+					displacer(self.wishbone.we_i, adr_offset, data_we, 2**offsetbits)
 				)
 			),
 			If(write_to_asmi,

migen/corelogic/misc.py

@@ -50,7 +50,7 @@ def displacer(signal, shift, output, n=None):
 def chooser(signal, shift, output, n=None):
 	if n is None:
 		n = 2**shift.bv.width
-	w = signal.bv.width
-	cases = [[Constant(i, shift.bv), output.eq(signal[i*w:i*(w+1)])] for i in range(n)]
+	w = output.bv.width
+	cases = [[Constant(i, shift.bv), output.eq(signal[i*w:(i+1)*w])] for i in range(n)]
 	cases[n-1][0] = Default()
 	return Case(shift, *cases)