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Fix syntax errors and other stupid problems

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This commit is contained in:
Sebastien Bourdeauducq 2012-02-13 22:28:02 +01:00
parent 8a61d9d121
commit 264be80f2d
3 changed files with 10 additions and 7 deletions
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9
migen/bus/asmibus.py
View file

@ -25,7 +25,7 @@ class Slot:
comb = [] comb = []
sync = [ sync = [
If(self.allocate, If(self.allocate,
self.state.eq(SLOT_PENDING) self.state.eq(SLOT_PENDING),
self.we.eq(self.allocate_we), self.we.eq(self.allocate_we),
self.adr.eq(self.allocate_adr) self.adr.eq(self.allocate_adr)
), ),
@ -39,7 +39,7 @@ class Slot:
sync += [ sync += [
If(self.allocate, If(self.allocate,
self._counter.eq(self.time) self._counter.eq(self.time)
).Elif(self._counter.eq != 0, ).Elif(self._counter != 0,
self._counter.eq(self._counter - 1) self._counter.eq(self._counter - 1)
) )
] ]
@ -68,6 +68,7 @@ class Port:
def finalize(self, tagbits, base): def finalize(self, tagbits, base):
if self.finalized: if self.finalized:
raise FinalizeError raise FinalizeError
self.finalized = True
self.tagbits = tagbits self.tagbits = tagbits
self.base = base self.base = base
nslots = len(self.slots) nslots = len(self.slots)
@ -121,7 +122,9 @@ class Hub:
def get_port(self, nslots=1): def get_port(self, nslots=1):
if self.finalized: if self.finalized:
raise FinalizeError raise FinalizeError
self.ports.append(Port(self, nslots)) new_port = Port(self, nslots)
self.ports.append(new_port)
return new_port
def finalize(self): def finalize(self):
if self.finalized: if self.finalized:

4
migen/bus/wishbone2asmi.py
View file

@ -60,9 +60,9 @@ class WB2ASMI:
data_di.eq(self.asmiport.dat_r), data_di.eq(self.asmiport.dat_r),
data_we.eq(Replicate(1, adw//8)) data_we.eq(Replicate(1, adw//8))
).Else( ).Else(
data_di.eq(Replicate(self.wishbone.dat_i, adw//32), data_di.eq(Replicate(self.wishbone.dat_i, adw//32)),
If(self.wishbone.cyc_i & self.wishbone.stb_i & self.wishbone.ack_o, If(self.wishbone.cyc_i & self.wishbone.stb_i & self.wishbone.ack_o,
displacer(self.wishbone.we_i, adr_offset, data_we) displacer(self.wishbone.we_i, adr_offset, data_we, 2**offsetbits)
) )
), ),
If(write_to_asmi, If(write_to_asmi,

4
migen/corelogic/misc.py
View file

@ -50,7 +50,7 @@ def displacer(signal, shift, output, n=None):
def chooser(signal, shift, output, n=None): def chooser(signal, shift, output, n=None):
if n is None: if n is None:
n = 2**shift.bv.width n = 2**shift.bv.width
w = signal.bv.width w = output.bv.width
cases = [[Constant(i, shift.bv), output.eq(signal[i*w:i*(w+1)])] for i in range(n)] cases = [[Constant(i, shift.bv), output.eq(signal[i*w:(i+1)*w])] for i in range(n)]
cases[n-1][0] = Default() cases[n-1][0] = Default()
return Case(shift, *cases) return Case(shift, *cases)