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interconnect/axi/axi_lite_to_simple: Avoid combinatorial loop on ax.valid/ax.ready.

This commit is contained in:
Florent Kermarrec 2022-11-14 09:34:10 +01:00
parent 82127043c3
commit 269525862b
1 changed files with 2 additions and 2 deletions
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4
litex/soc/interconnect/axi/axi_lite.py
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@ -147,16 +147,16 @@ def axi_lite_to_simple(axi_lite, port_adr, port_dat_r, port_dat_w=None, port_we=
do_read.eq(axi_lite.ar.valid),
),
# Start reading/writing immediately not to waste a cycle.
axi_lite.aw.ready.eq(last_was_read | ~axi_lite.ar.valid),
axi_lite.ar.ready.eq(~last_was_read | ~axi_lite.aw.valid),
If(do_write,
port_adr.eq(axi_lite.aw.addr[adr_shift:]),
If(axi_lite.w.valid,
axi_lite.aw.ready.eq(1),
axi_lite.w.ready.eq(1),
NextState("SEND-WRITE-RESPONSE")
)
).Elif(do_read,
port_adr.eq(axi_lite.ar.addr[adr_shift:]),
axi_lite.ar.ready.eq(1),
NextState("SEND-READ-RESPONSE"),
)
)