cores/uart: rename BridgedUART to UARTEmulator and rework/simplify it. Also integrated it in SoCCore with uart_name="emulator"
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@ -13,13 +13,15 @@ from litex.soc.interconnect.csr_eventmanager import *
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from litex.soc.interconnect import stream
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from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge
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# RS232 PHY ----------------------------------------------------------------------------------------
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class RS232PHYInterface:
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class UARTInterface:
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def __init__(self):
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self.sink = stream.Endpoint([("data", 8)])
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self.sink = stream.Endpoint([("data", 8)])
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self.source = stream.Endpoint([("data", 8)])
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# RS232 PHY ----------------------------------------------------------------------------------------
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class RS232PHYInterface(UARTInterface):
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pass
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class RS232PHYRX(Module):
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def __init__(self, pads, tuning_word):
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@ -268,25 +270,21 @@ class UARTMultiplexer(Module):
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]
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self.comb += Case(self.sel, cases)
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class BridgedUart(UART):
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"""
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Creates a UART that's fully compatible with the existing
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UART class, except it adds a second UART that can be read
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over the Wishbone bridge.
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# UART Emulator ------------------------------------------------------------------------------------
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This allows a program on the other end of the Wishbone
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bridge to act as a terminal emulator on a board where
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the UART is otherwise used as a Wishbone bridge.
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class UARTEmulator(UART):
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"""
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def __init__(self, **kw):
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class BridgedUartPhy:
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def __init__(self):
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self.sink = stream.Endpoint([("data", 8)])
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self.source = stream.Endpoint([("data", 8)])
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class CrossoverPhy:
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def __init__(self, phy):
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self.source = phy.sink
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self.sink = phy.source
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phy = BridgedUartPhy()
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UART.__init__(self, phy, **kw)
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self.submodules.xover = UART(CrossoverPhy(phy))
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UART emulation over Wishbone bridge.
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Creates a fully compatible UART that can be used by the CPU as a regular UART and adds a second
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UART, cross-connected to the main one to allow terminal emulation over a Wishbone bridge.
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"""
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def __init__(self, **kwargs):
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uart_phy = UARTInterface()
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emul_phy = UARTInterface()
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UART.__init__(self, uart_phy, **kwargs)
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self.submodules.emul = UART(emul_phy)
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self.comb += [
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uart_phy.source.connect(emul_phy.sink),
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emul_phy.source.connect(uart_phy.sink)
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]
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@ -240,7 +240,9 @@ class SoCCore(Module):
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# Add UART
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if with_uart:
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if uart_stub:
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self.submodules.uart = uart.UARTStub()
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self.submodules.uart = uart.UARTStub()
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elif uart_name == "emulator":
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self.submodules.uart = uart.UARTEmulator()
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else:
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if uart_name == "jtag_atlantic":
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from litex.soc.cores.jtag import JTAGAtlantic
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