targets/sim: fix

2017-12-06 22:22:05 +01:00 · 2017-12-06 22:22:05 +01:00 · 27d37fa95d
parent 284b16e2c1
commit 27d37fa95d
1 changed files with 5 additions and 0 deletions
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@ -23,6 +23,11 @@ from liteeth.core.mac import LiteEthMAC
 from litex.build.sim.config import SimConfig

 class BaseSoC(SoCSDRAM):
+    interrupt_map = {
+        "uart": 2,
+    }
+    interrupt_map.update(SoCSDRAM.interrupt_map)
+
    def __init__(self, **kwargs):
        platform = sim.Platform()
        SoCSDRAM.__init__(self, platform,