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targets/sim: fix

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This commit is contained in:
Florent Kermarrec 2017-12-06 22:22:05 +01:00
parent 284b16e2c1
commit 27d37fa95d
1 changed files with 5 additions and 0 deletions
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5
litex/boards/targets/sim.py
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@ -23,6 +23,11 @@ from liteeth.core.mac import LiteEthMAC
from litex.build.sim.config import SimConfig
class BaseSoC(SoCSDRAM):
interrupt_map = {
"uart": 2,
}
interrupt_map.update(SoCSDRAM.interrupt_map)
def __init__(self, **kwargs):
platform = sim.Platform()
SoCSDRAM.__init__(self, platform,