Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets/sim: fix

This commit is contained in:
Florent Kermarrec 2017-12-06 22:22:05 +01:00
parent 284b16e2c1
commit 27d37fa95d
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
litex/boards/targets/sim.py
View File

@ -23,6 +23,11 @@ from liteeth.core.mac import LiteEthMAC
from litex.build.sim.config import SimConfig from litex.build.sim.config import SimConfig
class BaseSoC(SoCSDRAM): class BaseSoC(SoCSDRAM):
interrupt_map = {
"uart": 2,
}
interrupt_map.update(SoCSDRAM.interrupt_map)
def __init__(self, **kwargs): def __init__(self, **kwargs):
platform = sim.Platform() platform = sim.Platform()
SoCSDRAM.__init__(self, platform, SoCSDRAM.__init__(self, platform,