stream: Switch back to LiteX FIFO, but add an additional output buffer, seems to be working...
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@ -281,25 +281,29 @@ class _AsyncFIFOWrapper(LiteXModule):
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#from verilog_axis.axis_async_fifo import AXISAsyncFIFO
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#from verilog_axis.axis_async_fifo import AXISAsyncFIFO
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#AXISAsyncFIFO.add_sources(platform)
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#AXISAsyncFIFO.add_sources(platform)
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class AsyncFIFO(_AsyncFIFOWrapper):
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#class AsyncFIFO(_AsyncFIFOWrapper):
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def __init__(self, layout, depth=None, buffered=False):
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depth = 4 if depth is None else depth
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assert depth >= 4
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buffered = True
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_AsyncFIFOWrapper.__init__(self,
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layout = layout,
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depth = depth,
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buffered = buffered
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)
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#class AsyncFIFO(_FIFOWrapper):
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# def __init__(self, layout, depth=None, buffered=False):
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# def __init__(self, layout, depth=None, buffered=False):
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# depth = 4 if depth is None else depth
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# depth = 4 if depth is None else depth
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# assert depth >= 4
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# assert depth >= 4
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# _FIFOWrapper.__init__(self,
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# buffered = True
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# fifo_class = fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
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# _AsyncFIFOWrapper.__init__(self,
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# layout = layout,
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# layout = layout,
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# depth = depth)
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# depth = depth,
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# buffered = buffered
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# )
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class AsyncFIFO(_FIFOWrapper):
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def __init__(self, layout, depth=None, buffered=False):
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depth = 4 if depth is None else depth
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assert depth >= 4
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buffered = True # FIXME: Required on Efinix...
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_FIFOWrapper.__init__(self,
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fifo_class = fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
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layout = layout,
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depth = depth
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)
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# FIXME: Additional buffer required on Efinix...
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ClockDomainsRenamer("read")(BufferizeEndpoints({"source": DIR_SOURCE})(self))
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# ClockDomainCrossing ------------------------------------------------------------------------------
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# ClockDomainCrossing ------------------------------------------------------------------------------
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