elsewhere: do not create interface in default param

This commit is contained in:
Sebastien Bourdeauducq 2012-12-06 17:34:48 +01:00
parent 62187aa23d
commit 280a87ea69
2 changed files with 15 additions and 5 deletions

View File

@ -18,8 +18,10 @@ class Interconnect(SimpleInterconnect):
pass
class Initiator(PureSimulable):
def __init__(self, generator, bus=Interface()):
def __init__(self, generator, bus=None):
self.generator = generator
if bus is None:
bus = Interface()
self.bus = bus
self.transaction = None
self.done = False
@ -50,7 +52,7 @@ def _compute_page_bits(nwords):
return 0
class SRAM:
def __init__(self, mem_or_size, address, bus=Interface()):
def __init__(self, mem_or_size, address, bus=None):
if isinstance(mem_or_size, Memory):
assert(mem_or_size.width <= data_width)
self.mem = mem_or_size
@ -62,6 +64,8 @@ class SRAM:
self._page = RegisterField("page", page_bits)
else:
self._page = None
if bus is None:
bus = Interface()
self.bus = bus
def get_registers(self):

View File

@ -133,8 +133,10 @@ class Tap(PureSimulable):
self.handler(transaction)
class Initiator(PureSimulable):
def __init__(self, generator, bus=Interface()):
def __init__(self, generator, bus=None):
self.generator = generator
if bus is None:
bus = Interface()
self.bus = bus
self.transaction_start = 0
self.transaction = None
@ -178,7 +180,9 @@ class TargetModel:
return True
class Target(PureSimulable):
def __init__(self, model, bus=Interface()):
def __init__(self, model, bus=None):
if bus is None:
bus = Interface()
self.bus = bus
self.model = model
@ -195,12 +199,14 @@ class Target(PureSimulable):
bus.ack = 0
class SRAM:
def __init__(self, mem_or_size, bus=Interface()):
def __init__(self, mem_or_size, bus=None):
if isinstance(mem_or_size, Memory):
assert(mem_or_size.width <= 32)
self.mem = mem_or_size
else:
self.mem = Memory(32, mem_or_size//4)
if bus is None:
bus = Interface()
self.bus = bus
def get_fragment(self):