test: add make.py to replace static config.py file

This commit is contained in:
Florent Kermarrec 2015-02-22 23:39:51 +01:00
parent b1dee774cd
commit 282c9b9426
8 changed files with 117 additions and 126 deletions

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@ -1,20 +0,0 @@
LEDIR = ../
PYTHON = python3
CMD = PYTHONPATH=$(LEDIR) $(PYTHON)
test_regs:
$(CMD) test_regs.py
test_la:
$(CMD) test_la.py
test_udp:
$(CMD) test_udp.py
test_etherbone:
$(CMD) test_etherbone.py
test_tty:
$(CMD) test_tty.py

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@ -1,14 +0,0 @@
use_uart = 1
use_eth = 0
csr_csv_file = "./csr.csv"
busword = 32
debug_wb = False
if use_uart:
from litescope.host.driver.uart import LiteScopeUARTDriver
wb = LiteScopeUARTDriver(2, 921600, csr_csv_file, busword, debug_wb)
if use_eth:
from litescope.host.driver.etherbone import LiteScopeEtherboneDriver
wb = LiteScopeEtherboneDriver("192.168.1.40", 20000, csr_csv_file, debug_wb)

33
test/make.py Normal file
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@ -0,0 +1,33 @@
#!/usr/bin/env python3
import argparse, importlib
def _get_args():
parser = argparse.ArgumentParser()
parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
parser.add_argument("--port", default=2, help="UART port")
parser.add_argument("--baudrate", default=921600, help="UART baudrate")
parser.add_argument("--ip_address", default="192.168.1.40", help="Etherbone IP address")
parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port")
parser.add_argument("--busword", default=32, help="CSR busword")
parser.add_argument("test", nargs="+", help="specify a test")
return parser.parse_args()
if __name__ == "__main__":
args = _get_args()
if args.bridge == "uart":
from litescope.host.driver.uart import LiteScopeUARTDriver
wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
elif args.bridge == "etherbone":
from litescope.host.driver.etherbone import LiteScopeEtherboneDriver
wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
else:
ValueError("Invalid bridge {}".format(args.bridge))
def _import(name):
return importlib.import_module(name)
for test in args.test:
t = _import("test_"+test)
t.main(wb)

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@ -4,55 +4,57 @@ from liteeth.test.model.etherbone import *
SRAM_BASE = 0x02000000
import socket
sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
# test probe
packet = EtherbonePacket()
packet.pf = 1
packet.encode()
sock.sendto(bytes(packet), ("192.168.1.40", 20000))
time.sleep(0.01)
def main(wb):
sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
# test writes
writes_datas = [j for j in range(16)]
writes = EtherboneWrites(base_addr=SRAM_BASE, datas=writes_datas)
record = EtherboneRecord()
record.writes = writes
record.reads = None
record.bca = 0
record.rca = 0
record.rff = 0
record.cyc = 0
record.wca = 0
record.wff = 0
record.byte_enable = 0xf
record.wcount = len(writes_datas)
record.rcount = 0
# test probe
packet = EtherbonePacket()
packet.pf = 1
packet.encode()
sock.sendto(bytes(packet), ("192.168.1.40", 20000))
time.sleep(0.01)
packet = EtherbonePacket()
packet.records = [record]
packet.encode()
sock.sendto(bytes(packet), ("192.168.1.40", 20000))
time.sleep(0.01)
# test writes
writes_datas = [j for j in range(16)]
writes = EtherboneWrites(base_addr=SRAM_BASE, datas=writes_datas)
record = EtherboneRecord()
record.writes = writes
record.reads = None
record.bca = 0
record.rca = 0
record.rff = 0
record.cyc = 0
record.wca = 0
record.wff = 0
record.byte_enable = 0xf
record.wcount = len(writes_datas)
record.rcount = 0
# test reads
reads_addrs = [SRAM_BASE+4*j for j in range(16)]
reads = EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
record = EtherboneRecord()
record.writes = None
record.reads = reads
record.bca = 0
record.rca = 0
record.rff = 0
record.cyc = 0
record.wca = 0
record.wff = 0
record.byte_enable = 0xf
record.wcount = 0
record.rcount = len(reads_addrs)
packet = EtherbonePacket()
packet.records = [record]
packet.encode()
sock.sendto(bytes(packet), ("192.168.1.40", 20000))
time.sleep(0.01)
packet = EtherbonePacket()
packet.records = [record]
packet.encode()
sock.sendto(bytes(packet), ("192.168.1.40", 20000))
time.sleep(0.01)
# test reads
reads_addrs = [SRAM_BASE+4*j for j in range(16)]
reads = EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
record = EtherboneRecord()
record.writes = None
record.reads = reads
record.bca = 0
record.rca = 0
record.rff = 0
record.cyc = 0
record.wca = 0
record.wff = 0
record.byte_enable = 0xf
record.wcount = 0
record.rcount = len(reads_addrs)
packet = EtherbonePacket()
packet.records = [record]
packet.encode()
sock.sendto(bytes(packet), ("192.168.1.40", 20000))
time.sleep(0.01)

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@ -1,34 +1,24 @@
from config import *
import time
from litescope.host.driver.la import LiteScopeLADriver
la = LiteScopeLADriver(wb.regs, "la", debug=True)
wb.open()
regs = wb.regs
###
def main(wb):
la = LiteScopeLADriver(wb.regs, "la", debug=True)
conditions = {}
conditions = {
"udpsocdevel_mac_rx_cdc_source_stb" : 1
}
conditions = {
"core_udp_tx_fsm_state" : 1
}
conditions = {
"etherbonesocdevel_master_bus_stb" : 1,
"etherbonesocdevel_master_bus_we" : 0
}
la.configure_term(port=0, cond=conditions)
la.configure_sum("term")
# Run Logic Analyzer
la.run(offset=2048, length=4000)
wb.open()
regs = wb.regs
###
while not la.done():
pass
conditions = {}
la.configure_term(port=0, cond=conditions)
la.configure_sum("term")
# Run Logic Analyzer
la.run(offset=2048, length=4000)
la.upload()
la.save("dump.vcd")
while not la.done():
pass
###
wb.close()
la.upload()
la.save("dump.vcd")
###
wb.close()

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@ -1,14 +1,12 @@
from config import *
wb.open()
regs = wb.regs
###
regs.phy_crg_reset.write(1)
print("sysid : 0x%04x" %regs.identifier_sysid.read())
print("revision : 0x%04x" %regs.identifier_revision.read())
print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
SRAM_BASE = 0x02000000
wb.write(SRAM_BASE, [i for i in range(64)])
print(wb.read(SRAM_BASE, 64))
###
wb.close()
def main(wb):
wb.open()
regs = wb.regs
###
print("sysid : 0x%04x" %regs.identifier_sysid.read())
print("revision : 0x%04x" %regs.identifier_revision.read())
print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
SRAM_BASE = 0x02000000
wb.write(SRAM_BASE, [i for i in range(64)])
print(wb.read(SRAM_BASE, 64))
###
wb.close()

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@ -31,5 +31,6 @@ def test(fpga_ip, udp_port, test_message):
except KeyboardInterrupt:
pass
test_message = "LiteEth virtual TTY Hello world\n"
test("192.168.1.40", 10000, test_message)
def main(wb):
test_message = "LiteEth virtual TTY Hello world\n"
test("192.168.1.40", 10000, test_message)

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@ -76,5 +76,6 @@ def test(fpga_ip, udp_port, test_size):
except KeyboardInterrupt:
pass
test("192.168.1.40", 6000, 128*KB)
test("192.168.1.40", 8000, 128*KB)
def main(wb):
test("192.168.1.40", 6000, 128*KB)
test("192.168.1.40", 8000, 128*KB)