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cpu/picorv32: use a single idbus

This commit is contained in:
Florent Kermarrec 2019-10-10 22:02:04 +02:00
parent 5daf1a2296
commit 28517d20ca
1 changed files with 13 additions and 30 deletions
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43
litex/soc/cores/cpu/picorv32/core.py
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@ -58,9 +58,8 @@ class PicoRV32(CPU):
self.platform = platform self.platform = platform
self.variant = variant self.variant = variant
self.reset = Signal() self.reset = Signal()
self.ibus = i = wishbone.Interface() self.idbus = idbus = wishbone.Interface()
self.dbus = d = wishbone.Interface() self.buses = [idbus]
self.buses = [i, d]
self.interrupt = Signal(32) self.interrupt = Signal(32)
self.trap = Signal() self.trap = Signal()
@ -154,33 +153,17 @@ class PicoRV32(CPU):
# adapt memory interface to wishbone # adapt memory interface to wishbone
self.comb += [ self.comb += [
# instruction # instruction
i.adr.eq(mem_addr[2:]), idbus.adr.eq(mem_addr[2:]),
i.dat_w.eq(mem_wdata), idbus.dat_w.eq(mem_wdata),
i.we.eq(mem_wstrb != 0), idbus.we.eq(mem_wstrb != 0),
i.sel.eq(mem_wstrb), idbus.sel.eq(mem_wstrb),
i.cyc.eq(mem_valid & mem_instr), idbus.cyc.eq(mem_valid),
i.stb.eq(mem_valid & mem_instr), idbus.stb.eq(mem_valid),
i.cti.eq(0), idbus.cti.eq(0),
i.bte.eq(0), idbus.bte.eq(0),
If(mem_instr, mem_ready.eq(idbus.ack),
mem_ready.eq(i.ack), mem_rdata.eq(idbus.dat_r),
mem_rdata.eq(i.dat_r),
),
# data
d.adr.eq(mem_addr[2:]),
d.dat_w.eq(mem_wdata),
d.we.eq(mem_wstrb != 0),
d.sel.eq(mem_wstrb),
d.cyc.eq(mem_valid & ~mem_instr),
d.stb.eq(mem_valid & ~mem_instr),
d.cti.eq(0),
d.bte.eq(0),
If(~mem_instr,
mem_ready.eq(d.ack),
mem_rdata.eq(d.dat_r)
)
] ]
# add verilog sources # add verilog sources