cpu/rocket: parameterize axi interface data width

Rocket variants can be configured with axi port data widths that
are multiples of the native word size (64 bits in our case). In
the future, we will add variants with mem_axi data width > 64 bit,
to match the native data width of the LiteDRAM controller on
various development boards (e.g., 128 bits on the ecp5versa, and
256 bits on the trellisboard).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

litex/soc/cores/cpu/rocket/core.py

@@ -50,6 +50,13 @@ GCC_FLAGS = {
     "full":     "-march=rv64imafdc -mabi=lp64 ",
 }
 
+AXI_DATA_WIDTHS = {
+    # variant : (mem, mmio)
+    "standard": ( 64,  64),
+    "linux":    ( 64,  64),
+    "full":     ( 64,  64),
+}
+
 class RocketRV64(CPU):
     name                 = "rocket"
     data_width           = 64
@@ -85,10 +92,12 @@ class RocketRV64(CPU):
         self.reset     = Signal()
         self.interrupt = Signal(4)
 
-        self.mem_axi   =  mem_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
-        self.mmio_axi  = mmio_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
+        mem_dw, mmio_dw = AXI_DATA_WIDTHS[self.variant]
 
-        self.mmio_wb   = mmio_wb = wishbone.Interface(data_width=64, adr_width=29)
+        self.mem_axi   =  mem_axi = axi.AXIInterface(data_width= mem_dw, address_width=32, id_width=4)
+        self.mmio_axi  = mmio_axi = axi.AXIInterface(data_width=mmio_dw, address_width=32, id_width=4)
+
+        self.mmio_wb   = mmio_wb = wishbone.Interface(data_width=mmio_dw, adr_width=32-log2_int(mmio_dw//8))
 
         self.buses     = [mmio_wb]