README: update
This commit is contained in:
parent
05c7b9daf4
commit
28cd2da24e
6
README
6
README
|
@ -9,10 +9,8 @@
|
||||||
|
|
||||||
[> Intro
|
[> Intro
|
||||||
--------
|
--------
|
||||||
LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
|
LiteX is a FPGA design/SoC builder that can be used to build cores, create
|
||||||
our cores, integrate them in complete SoC and load/flash them to the hardware
|
SoCs and full FPGA designs.
|
||||||
and experiment new features. (structure is kept close to MiSoC to ease
|
|
||||||
collaboration)
|
|
||||||
|
|
||||||
Typical LiteX design flow:
|
Typical LiteX design flow:
|
||||||
--------------------------
|
--------------------------
|
||||||
|
|
Loading…
Reference in New Issue