soc/cores/cpu/zynqmp/core.py: added missing pps signals

2024-10-10 17:26:35 +02:00 · 2024-10-10 17:26:35 +02:00 · 2935b7afb1
parent dc3364a3c7
commit 2935b7afb1
1 changed files with 1 additions and 0 deletions
--- a/litex/soc/cores/cpu/zynqmp/core.py
+++ b/litex/soc/cores/cpu/zynqmp/core.py
@ -55,6 +55,7 @@ class ZynqMP(CPU):
        self.i2c_use        = []          # I2c reserved ports.
        self.uart_use       = []          # UART reserved ports.
        self.can_use        = []          # CAN reserved/used ports.
+        self.pps            = Signal(4)   # Optional PPS (with gemX and PTP enabled)

        # [ 7: 0]: PL_PS_Group0 [128:121]
        # [15: 8]: PL_PS_Group1 [143:136]