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soc/cores/cpu/zynqmp/core.py: added missing pps signals

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Gwenhael Goavec-Merou 2024-10-10 17:26:35 +02:00
parent dc3364a3c7
commit 2935b7afb1
1 changed files with 1 additions and 0 deletions
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litex/soc/cores/cpu/zynqmp/core.py
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@ -55,6 +55,7 @@ class ZynqMP(CPU):
self.i2c_use = [] # I2c reserved ports. self.i2c_use = [] # I2c reserved ports.
self.uart_use = [] # UART reserved ports. self.uart_use = [] # UART reserved ports.
self.can_use = [] # CAN reserved/used ports. self.can_use = [] # CAN reserved/used ports.
self.pps = Signal(4) # Optional PPS (with gemX and PTP enabled)
# [ 7: 0]: PL_PS_Group0 [128:121] # [ 7: 0]: PL_PS_Group0 [128:121]
# [15: 8]: PL_PS_Group1 [143:136] # [15: 8]: PL_PS_Group1 [143:136]