soc/interconnect/packet: simplify/refactor Packetizer/Depacketizer to keep it simple
To avoid complex FSMs, let the synthesis tool do the simplifications when the FSM states are not reachable.
This commit is contained in:
Florent Kermarrec
parent
33c4d961b5
commit
2946581e50
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@ -156,274 +156,230 @@ class Header:
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class Packetizer(Module):
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def __init__(self, sink_description, source_description, header):
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self.sink = sink = stream.Endpoint(sink_description)
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self.sink = sink = stream.Endpoint(sink_description)
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self.source = source = stream.Endpoint(source_description)
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self.header = Signal(header.length*8)
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# # #
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dw = len(self.sink.data)
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cw = dw // 8
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header_reg = Signal(header.length*8, reset_less=True)
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header_words = (header.length*8)//dw
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header_residue = header.length % cw
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if header_residue:
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header_leftover = Signal(header_residue*8)
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load = Signal()
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shift = Signal()
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counter = Signal(max=max(header_words, 2))
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counter_reset = Signal()
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counter_ce = Signal()
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self.sync += \
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If(counter_reset,
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counter.eq(0)
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).Elif(counter_ce,
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counter.eq(counter + 1)
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)
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# Parameters -------------------------------------------------------------------------------
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data_width = len(self.sink.data)
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bytes_per_clk = data_width//8
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header_words = (header.length*8)//data_width
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header_leftover = header.length%bytes_per_clk
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# Signals ----------------------------------------------------------------------------------
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sr = Signal(header.length*8, reset_less=True)
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sr_load = Signal()
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sr_shift = Signal()
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count = Signal(max=max(header_words, 2))
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sink_d = stream.Endpoint(sink_description)
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# Header Encode/Load/Shift -----------------------------------------------------------------
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self.comb += header.encode(sink, self.header)
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if header_words == 1:
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self.sync += [
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If(load,
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header_reg.eq(self.header)
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)
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]
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else:
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self.sync += [
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If(load,
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header_reg.eq(self.header)
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).Elif(shift,
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header_reg.eq(Cat(header_reg[dw:], Signal(dw)))
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)
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.transitioning = transitioning = Signal() # TODO: Perhaps fsm already has a transitioning signal
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# TODO: What is the recommended way to delay a record, a FIFO?
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last_buf, valid_buf = Signal(), Signal()
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self.data_buf = data_buf = Signal(len(sink.data))
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if header_words == 1 and header_residue == 0:
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idle_next_state = "COPY"
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elif header_words == 1 and header_residue:
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idle_next_state = "STAGGERCOPY"
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else:
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idle_next_state = "SEND_HEADER"
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self.sync += [
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If(sr_load,
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sr.eq(self.header)
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).Elif(sr_shift,
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sr.eq(sr[data_width:])
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)
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]
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# FSM --------------------------------------------------------------------------------------
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm_from_idle = Signal()
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fsm.act("IDLE",
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sink.ready.eq(1),
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counter_reset.eq(1),
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NextValue(count, 1),
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If(sink.valid,
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sink.ready.eq(0),
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source.valid.eq(1),
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source.last.eq(0),
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source.data.eq(self.header[:dw]),
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If(source.valid & source.ready,
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load.eq(1),
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NextValue(transitioning, 1),
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NextState(idle_next_state)
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sink.ready.eq(0),
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source.valid.eq(1),
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source.last.eq(0),
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source.data.eq(self.header[:data_width]),
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If(source.valid & source.ready,
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sr_load.eq(1),
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NextValue(fsm_from_idle, 1),
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If(header_words == 1,
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If(header_leftover != 0,
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NextState("UNALIGNED-DATA-COPY")
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).Else(
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NextState("ALIGNED-DATA-COPY")
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)
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).Else(
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NextState("HEADER-SEND")
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)
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)
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)
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)
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# if header_residue and header_words >= 2:
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# self.sync += [header_leftover.eq(header_reg[2*dw:(2*dw+header_residue*8)]),
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# ]
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self.sync += [last_buf.eq(sink.last),
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data_buf.eq(sink.data),
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valid_buf.eq(sink.valid),
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]
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if header_words != 1:
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fsm.act("SEND_HEADER",
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source.valid.eq(1),
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source.last.eq(0),
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source.data.eq(header_reg[dw:2*dw]),
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If(source.valid & source.ready,
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shift.eq(1),
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counter_ce.eq(1),
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If(counter == header_words-2,
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shift.eq(0),
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counter_ce.eq(1 if header_residue else 0),
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NextValue(transitioning, 1),
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NextState("STAGGERCOPY" if header_residue else "COPY")
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)
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fsm.act("HEADER-SEND",
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source.valid.eq(1),
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source.last.eq(0),
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source.data.eq(sr[data_width:]),
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If(source.valid & source.ready,
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sr_shift.eq(1),
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If(count == (header_words - 1),
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sr_shift.eq(0),
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If(header_leftover,
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NextState("UNALIGNED-DATA-COPY"),
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NextValue(count, count + 1)
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).Else(
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NextState("ALIGNED-DATA-COPY")
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)
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).Else(
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NextValue(count, count + 1),
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)
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)
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)
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fsm.act("ALIGNED-DATA-COPY",
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source.valid.eq(sink.valid),
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source.last.eq(sink.last),
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source.data.eq(sink.data),
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If(source.valid & source.ready,
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sink.ready.eq(1),
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If(source.last,
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NextState("IDLE")
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)
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)
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)
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header_offset_multiplier = 1 if header_words == 1 else 2
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self.sync += If(source.valid & source.ready, sink_d.eq(sink))
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fsm.act("UNALIGNED-DATA-COPY",
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source.valid.eq(sink_d.valid),
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source.last.eq(sink_d.last),
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If(fsm_from_idle,
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source.data[:header_leftover*8].eq(sr[header_offset_multiplier*data_width:])
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).Else(
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source.data[:header_leftover*8].eq(sink_d.data[(bytes_per_clk-header_leftover)*8:])
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),
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source.data[header_leftover*8:].eq(sink.data),
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If(source.valid & source.ready,
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sink.ready.eq(1),
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If(sink.valid, NextValue(fsm_from_idle, 0)),
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If(source.last,
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NextState("IDLE")
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)
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)
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)
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# Error ------------------------------------------------------------------------------------
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if hasattr(sink, "error"):
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self.comb += source.error.eq(sink.error)
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if hasattr(sink, "last_be"):
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# header_lengh + last_be
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cw = dw//8
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rotate_by = header.length % cw
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x = [sink.last_be[(i + rotate_by) % cw] for i in range(cw)]
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self.comb += source.last_be.eq(Cat(*x))
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if header_residue:
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header_offset_multiplier = hom = 1 if header_words == 1 else 2
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fsm.act("STAGGERCOPY",
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source.valid.eq(valid_buf),
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source.last.eq(last_buf),
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If(transitioning,
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source.data.eq(Cat(header_reg[hom*dw:hom*dw+header_residue*8],
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sink.data[:(cw-header_residue)*8]))
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).Else(
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source.data.eq(Cat(data_buf[(cw-header_residue)*8:],
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sink.data[:(cw-header_residue)*8]))
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),
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If(source.valid & source.ready,
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sink.ready.eq(1),
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If(sink.valid,
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NextValue(transitioning, 0)
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),
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If(source.last,
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NextState("IDLE")
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)
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),
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)
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else:
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fsm.act("COPY",
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source.valid.eq(sink.valid),
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source.last.eq(sink.last),
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source.data.eq(sink.data),
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If(source.valid & source.ready,
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NextValue(transitioning, 0),
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sink.ready.eq(1),
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If(source.last,
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NextState("IDLE")
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)
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),
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)
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# Last BE ----------------------------------------------------------------------------------
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if hasattr(sink, "last_be"):
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rotate_by = header.length%bytes_per_clk
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x = [sink.last_be[(i + rotate_by)%bytes_per_clk] for i in range(bytes_per_clk)]
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self.comb += source.last_be.eq(Cat(*x))
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# Depacketizer -------------------------------------------------------------------------------------
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class Depacketizer(Module):
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def __init__(self, sink_description, source_description, header):
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self.sink = sink = stream.Endpoint(sink_description)
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self.sink = sink = stream.Endpoint(sink_description)
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self.source = source = stream.Endpoint(source_description)
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self.header = Signal(header.length*8)
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# # #
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dw = len(sink.data)
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# Parameters -------------------------------------------------------------------------------
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data_width = len(sink.data)
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bytes_per_clk = data_width// 8
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header_words = (header.length*8)//data_width
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header_leftover = header.length%bytes_per_clk
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cw = dw // 8
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# Signals ----------------------------------------------------------------------------------
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sr = Signal(header.length*8, reset_less=True)
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sr_shift = Signal()
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sr_shift_leftover = Signal()
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no_payload = Signal()
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count = Signal(max=max(header_words, 2))
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sink_d = stream.Endpoint(sink_description)
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header_reg = Signal(header.length*8, reset_less=True)
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header_words = (header.length*8)//dw
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header_residue = header.length % cw
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shift = Signal()
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counter = Signal(max=max(header_words, 2))
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counter_reset = Signal()
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counter_ce = Signal()
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self.sync += \
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If(counter_reset,
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counter.eq(0)
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).Elif(counter_ce,
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counter.eq(counter + 1)
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# Header Shift/Decode ----------------------------------------------------------------------
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self.sync += [
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If((header_words == 1) & (header_leftover == 0),
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If(sr_shift, sr.eq(sink.data))
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).Else(
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If(sr_shift, sr.eq(Cat(sr[bytes_per_clk*8:], sink.data))),
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If(sr_shift_leftover, sr.eq(Cat(sr[header_leftover*8:], sink.data)))
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)
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]
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self.comb += self.header.eq(sr)
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self.comb += header.decode(self.header, source)
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if header_words == 1 and header_residue == 0:
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self.sync += \
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If(shift,
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header_reg.eq(sink.data)
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)
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else:
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self.sync += \
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If(shift,
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header_reg.eq(Cat(header_reg[dw:], sink.data))
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)
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self.comb += self.header.eq(header_reg)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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# TODO: Perhaps fsm already has a transitioning signal
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self.transitioning = transitioning = Signal()
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last_buf, valid_buf = Signal(), Signal()
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self.data_buf = data_buf = Signal(len(sink.data))
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if header_words == 1 and header_residue == 0:
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idle_next_state = "COPY"
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elif header_words == 1 and header_residue:
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idle_next_state = "STAGGERCOPY"
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else:
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idle_next_state = "RECEIVE_HEADER"
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# FSM --------------------------------------------------------------------------------------
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm_from_idle = Signal()
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fsm.act("IDLE",
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sink.ready.eq(1),
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counter_reset.eq(1),
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NextValue(count, 1),
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If(sink.valid,
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shift.eq(1),
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NextValue(transitioning, 1),
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NextState(idle_next_state)
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sr_shift.eq(1),
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NextValue(fsm_from_idle, 1),
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If(header_words == 1,
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NextValue(no_payload, sink.last),
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If(header_leftover,
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NextState("UNALIGNED-DATA-COPY")
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).Else(
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NextState("ALIGNED-DATA-COPY")
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),
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).Else(
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NextState("HEADER-RECEIVE")
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)
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)
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)
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self.sync += [If(sink.ready, data_buf.eq(sink.data)),
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valid_buf.eq(sink.valid),
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]
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if header_words != 1:
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fsm.act("RECEIVE_HEADER",
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sink.ready.eq(1),
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If(sink.valid,
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counter_ce.eq(1),
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shift.eq(1),
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If(counter == header_words-2,
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counter_ce.eq(1 if header_residue else 0),
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NextValue(transitioning, 1),
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NextState("STAGGERCOPY" if header_residue else "COPY")
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fsm.act("HEADER-RECEIVE",
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sink.ready.eq(1),
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If(sink.valid,
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NextValue(count, count + 1),
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sr_shift.eq(1),
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If(count == (header_words - 1),
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NextValue(no_payload, sink.last),
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If(header_leftover,
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NextValue(count, count + 1),
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NextState("UNALIGNED-DATA-COPY")
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).Else(
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NextState("ALIGNED-DATA-COPY")
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)
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)
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)
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no_payload = Signal()
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self.sync += \
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If(fsm.before_entering("COPY") | fsm.before_entering("STAGGERCOPY"),
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no_payload.eq(sink.last)
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)
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self.sync += If(sink.valid & sink.ready, sink_d.eq(sink))
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fsm.act("UNALIGNED-DATA-COPY",
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source.valid.eq((sink.valid & ~fsm_from_idle) | no_payload),
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source.last.eq(sink.last | no_payload),
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sink.ready.eq(source.ready),
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If(sink.valid & sink.ready,
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NextValue(fsm_from_idle, 0),
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If(fsm_from_idle,
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sr_shift_leftover.eq(1),
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).Else(
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source.data.eq(sink_d.data[header_leftover*8:]),
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source.data[(bytes_per_clk-header_leftover)*8:].eq(sink.data)
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),
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If(source.last,
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NextState("IDLE")
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)
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)
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)
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fsm.act("ALIGNED-DATA-COPY",
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source.last.eq(sink.last | no_payload),
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source.data.eq(sink.data),
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sink.ready.eq(source.ready),
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source.valid.eq(sink.valid | no_payload),
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If(source.valid & source.ready,
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If(source.last,
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NextState("IDLE")
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)
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)
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)
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# Error ------------------------------------------------------------------------------------
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if hasattr(sink, "error"):
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self.comb += source.error.eq(sink.error)
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# Last BE ----------------------------------------------------------------------------------
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if hasattr(sink, "last_be"):
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# header_lengh + last_be
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cw = dw//8
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x = [sink.last_be[(i - (cw - header_residue)) % cw] for i in range(cw)]
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x = [sink.last_be[(i - (bytes_per_clk - header_leftover))%bytes_per_clk]
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for i in range(bytes_per_clk)]
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self.comb += source.last_be.eq(Cat(*x))
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self.comb += [
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header.decode(self.header, source)
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]
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if header_residue:
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fsm.act("STAGGERCOPY",
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source.last.eq(sink.last | no_payload),
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sink.ready.eq(source.ready),
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source.valid.eq(sink.valid & ~transitioning | no_payload),
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If(sink.valid & source.ready,
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If(transitioning,
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NextValue(header_reg, Cat(header_reg[header_residue*8:],
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sink.data[:header_residue*8]))
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).Else(
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source.data.eq(Cat(data_buf[header_residue*8:],
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sink.data[:header_residue*8])),
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),
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NextValue(transitioning, 0)
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),
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If(source.valid & source.ready & source.last,
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NextState("IDLE")
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),
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)
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else:
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fsm.act("COPY",
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source.last.eq(sink.last | no_payload),
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source.data.eq(sink.data),
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sink.ready.eq(source.ready),
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source.valid.eq(sink.valid | no_payload),
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If(source.valid & source.ready,
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NextValue(transitioning, 0),
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If(source.last,
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NextState("IDLE")
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)
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)
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)
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