phy: use primitives dict and use only sata.std
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30964db4a1
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294855e292
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@ -4,7 +4,7 @@ from migen.fhdl.std import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.fsm import FSM, NextState
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from lib.sata.k7sataphy.std import *
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from lib.sata.std import *
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from lib.sata.k7sataphy.gtx import GTXE2_COMMON
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class K7SATAPHYCRG(Module):
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@ -58,7 +58,7 @@ class K7SATAPHYCRG(Module):
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p_BANDWIDTH="HIGH", p_COMPENSATION="ZHOLD", i_RST=mmcm_reset, o_LOCKED=mmcm_locked,
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# DRP
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i_DCLK=0, i_DEN=0, i_DWE=0, #o_DRDY=,
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i_DCLK=0, i_DEN=0, i_DWE=0, #o_DRDY=,
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i_DADDR=0, i_DI=0, #o_DO=,
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# VCO
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@ -5,7 +5,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.fsm import FSM, NextState
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from migen.flow.actor import Sink, Source
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from lib.sata.k7sataphy.std import *
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from lib.sata.std import *
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def us(t, clk_freq):
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clk_period_us = 1000000/clk_freq
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@ -117,7 +117,7 @@ class K7SATAPHYHostCtrl(Module):
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)
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fsm.act("SEND_ALIGN",
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gtx.txelecidle.eq(0),
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self.source.data.eq(ALIGN_VAL),
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self.source.data.eq(primitives["ALIGN"]),
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self.source.charisk.eq(0b0001),
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If(non_align_cnt == 3,
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NextState("READY")
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@ -125,7 +125,7 @@ class K7SATAPHYHostCtrl(Module):
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)
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fsm.act("READY",
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gtx.txelecidle.eq(0),
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self.source.data.eq(SYNC_VAL),
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self.source.data.eq(primitives["SYNC"]),
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self.source.charisk.eq(0b0001),
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self.ready.eq(1),
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)
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@ -139,7 +139,7 @@ class K7SATAPHYHostCtrl(Module):
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gtx.txcomwake.eq(txcomwake & ~txcomwake_d),
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]
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self.comb += align_detect.eq(self.sink.stb & (self.sink.data == ALIGN_VAL));
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self.comb += align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"]));
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self.sync += \
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If(fsm.ongoing("RESET"),
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align_timeout_cnt.eq(us(873, clk_freq))
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@ -254,7 +254,7 @@ class K7SATAPHYDeviceCtrl(Module):
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fsm.act("SEND_ALIGN",
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gtx.txelecidle.eq(0),
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gtx.rxalign.eq(1),
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self.source.data.eq(ALIGN_VAL),
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self.source.data.eq(primitives["ALIGN"]),
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self.source.charisk.eq(0b0001),
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If(align_detect,
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NextState("READY")
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@ -284,7 +284,7 @@ class K7SATAPHYDeviceCtrl(Module):
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gtx.txcomwake.eq(txcomwake & ~txcomwake_d),
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]
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self.comb += align_detect.eq(self.sink.stb & (self.sink.data == ALIGN_VAL));
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self.comb += align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"]));
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self.sync += \
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If(fsm.ongoing("RESET"),
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align_timeout_cnt.eq(us(55, clk_freq))
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@ -3,7 +3,7 @@ from migen.genlib.misc import chooser
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from migen.actorlib.fifo import AsyncFIFO
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from migen.flow.actor import Sink, Source
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from lib.sata.k7sataphy.std import *
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from lib.sata.std import *
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class K7SATAPHYDatapathRX(Module):
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def __init__(self):
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@ -143,7 +143,7 @@ class K7SATAPHYDatapath(Module):
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If(ctrl.ready,
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If(send_align,
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tx.sink.stb.eq(1),
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tx.sink.data.eq(ALIGN_VAL),
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tx.sink.data.eq(primitives["ALIGN"]),
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tx.sink.charisk.eq(0b0001),
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self.sink.ack.eq(0)
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).Else(
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@ -1,7 +1,7 @@
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from migen.fhdl.std import *
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from migen.genlib.cdc import *
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from lib.sata.k7sataphy.std import *
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from lib.sata.std import *
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class _PulseSynchronizer(PulseSynchronizer):
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def __init__(self, i, idomain, o, odomain):
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@ -1,8 +0,0 @@
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from migen.fhdl.std import *
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from migen.genlib.record import *
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ALIGN_VAL = 0x7B4A4ABC
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SYNC_VAL = 0xB5B5957C
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def ones(width):
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return 2**width-1
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@ -1,18 +1,24 @@
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from migen.fhdl.std import *
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from migen.genlib.record import *
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ALIGN_VAL = 0x7B4A4ABC
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SYNC_VAL = 0xB5B5957C
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R_RDY_VAL = 0x4A4A957C
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R_OK_VAL = 0x3535B57C
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R_ERR_VAL = 0x5656B57C
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R_IP_VAL = 0X5555B57C
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X_RDY_VAL = 0x5757B57C
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CONT_VAL = 0x9999AA7C
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WTRM_VAL = 0x5858B57C
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SOF_VAL = 0x3737B57C
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EOF_VAL = 0xD5D5B57C
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HOLD_VAL = 0xD5D5AA7C
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HOLD_ACK = 0X9595AA7C
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primitives = {
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"ALIGN" : 0x7B4A4ABC,
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"SYNC" : 0xB5B5957C,
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"R_RDY" : 0x4A4A957C,
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"R_OK" : 0x3535B57C,
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"R_ERR" : 0x5656B57C,
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"R_IP" : 0X5555B57C,
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"X_RDY" : 0x5757B57C,
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"CONT" : 0x9999AA7C,
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"WTRM" : 0x5858B57C,
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"SOF" : 0x3737B57C,
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"EOF" : 0xD5D5B57C,
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"HOLD" : 0xD5D5AA7C,
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"HOLD" : 0X9595AA7C
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}
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def ones(width):
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return 2**width-1
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def phy_layout(dw):
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layout = [
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