phy: use primitives dict and use only sata.std

This commit is contained in:
Florent Kermarrec 2014-11-11 10:19:24 +01:00
parent 30964db4a1
commit 294855e292
6 changed files with 30 additions and 32 deletions

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@ -4,7 +4,7 @@ from migen.fhdl.std import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.fsm import FSM, NextState
from lib.sata.k7sataphy.std import *
from lib.sata.std import *
from lib.sata.k7sataphy.gtx import GTXE2_COMMON
class K7SATAPHYCRG(Module):

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@ -5,7 +5,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.fsm import FSM, NextState
from migen.flow.actor import Sink, Source
from lib.sata.k7sataphy.std import *
from lib.sata.std import *
def us(t, clk_freq):
clk_period_us = 1000000/clk_freq
@ -117,7 +117,7 @@ class K7SATAPHYHostCtrl(Module):
)
fsm.act("SEND_ALIGN",
gtx.txelecidle.eq(0),
self.source.data.eq(ALIGN_VAL),
self.source.data.eq(primitives["ALIGN"]),
self.source.charisk.eq(0b0001),
If(non_align_cnt == 3,
NextState("READY")
@ -125,7 +125,7 @@ class K7SATAPHYHostCtrl(Module):
)
fsm.act("READY",
gtx.txelecidle.eq(0),
self.source.data.eq(SYNC_VAL),
self.source.data.eq(primitives["SYNC"]),
self.source.charisk.eq(0b0001),
self.ready.eq(1),
)
@ -139,7 +139,7 @@ class K7SATAPHYHostCtrl(Module):
gtx.txcomwake.eq(txcomwake & ~txcomwake_d),
]
self.comb += align_detect.eq(self.sink.stb & (self.sink.data == ALIGN_VAL));
self.comb += align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"]));
self.sync += \
If(fsm.ongoing("RESET"),
align_timeout_cnt.eq(us(873, clk_freq))
@ -254,7 +254,7 @@ class K7SATAPHYDeviceCtrl(Module):
fsm.act("SEND_ALIGN",
gtx.txelecidle.eq(0),
gtx.rxalign.eq(1),
self.source.data.eq(ALIGN_VAL),
self.source.data.eq(primitives["ALIGN"]),
self.source.charisk.eq(0b0001),
If(align_detect,
NextState("READY")
@ -284,7 +284,7 @@ class K7SATAPHYDeviceCtrl(Module):
gtx.txcomwake.eq(txcomwake & ~txcomwake_d),
]
self.comb += align_detect.eq(self.sink.stb & (self.sink.data == ALIGN_VAL));
self.comb += align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"]));
self.sync += \
If(fsm.ongoing("RESET"),
align_timeout_cnt.eq(us(55, clk_freq))

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@ -3,7 +3,7 @@ from migen.genlib.misc import chooser
from migen.actorlib.fifo import AsyncFIFO
from migen.flow.actor import Sink, Source
from lib.sata.k7sataphy.std import *
from lib.sata.std import *
class K7SATAPHYDatapathRX(Module):
def __init__(self):
@ -143,7 +143,7 @@ class K7SATAPHYDatapath(Module):
If(ctrl.ready,
If(send_align,
tx.sink.stb.eq(1),
tx.sink.data.eq(ALIGN_VAL),
tx.sink.data.eq(primitives["ALIGN"]),
tx.sink.charisk.eq(0b0001),
self.sink.ack.eq(0)
).Else(

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@ -1,7 +1,7 @@
from migen.fhdl.std import *
from migen.genlib.cdc import *
from lib.sata.k7sataphy.std import *
from lib.sata.std import *
class _PulseSynchronizer(PulseSynchronizer):
def __init__(self, i, idomain, o, odomain):

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@ -1,8 +0,0 @@
from migen.fhdl.std import *
from migen.genlib.record import *
ALIGN_VAL = 0x7B4A4ABC
SYNC_VAL = 0xB5B5957C
def ones(width):
return 2**width-1

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@ -1,18 +1,24 @@
from migen.fhdl.std import *
from migen.genlib.record import *
ALIGN_VAL = 0x7B4A4ABC
SYNC_VAL = 0xB5B5957C
R_RDY_VAL = 0x4A4A957C
R_OK_VAL = 0x3535B57C
R_ERR_VAL = 0x5656B57C
R_IP_VAL = 0X5555B57C
X_RDY_VAL = 0x5757B57C
CONT_VAL = 0x9999AA7C
WTRM_VAL = 0x5858B57C
SOF_VAL = 0x3737B57C
EOF_VAL = 0xD5D5B57C
HOLD_VAL = 0xD5D5AA7C
HOLD_ACK = 0X9595AA7C
primitives = {
"ALIGN" : 0x7B4A4ABC,
"SYNC" : 0xB5B5957C,
"R_RDY" : 0x4A4A957C,
"R_OK" : 0x3535B57C,
"R_ERR" : 0x5656B57C,
"R_IP" : 0X5555B57C,
"X_RDY" : 0x5757B57C,
"CONT" : 0x9999AA7C,
"WTRM" : 0x5858B57C,
"SOF" : 0x3737B57C,
"EOF" : 0xD5D5B57C,
"HOLD" : 0xD5D5AA7C,
"HOLD" : 0X9595AA7C
}
def ones(width):
return 2**width-1
def phy_layout(dw):
layout = [