examples/sim: rename abstract_transactions to abstract_transactions_wb, use new APIs, remove ASMI
This commit is contained in:
Sebastien Bourdeauducq
parent
35f9f2e9d7
commit
2948f6a16a
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from random import Random
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from migen.fhdl.std import *
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from migen.bus.transactions import *
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from migen.bus import wishbone, asmibus
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from migen.sim.generic import Simulator
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# Our bus master.
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# Python generators let us program bus transactions in an elegant sequential style.
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def my_generator():
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prng = Random(92837)
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# Write to the first addresses.
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for x in range(10):
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t = TWrite(x, 2*x)
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yield t
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print("Wrote in " + str(t.latency) + " cycle(s)")
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# Insert some dead cycles to simulate bus inactivity.
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for delay in range(prng.randrange(0, 3)):
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yield None
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# Read from the first addresses.
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for x in range(10):
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t = TRead(x)
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yield t
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print("Read " + str(t.data) + " in " + str(t.latency) + " cycle(s)")
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for delay in range(prng.randrange(0, 3)):
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yield None
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# Our bus slave.
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class MyModel:
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def read(self, address):
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return address + 4
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class MyModelWB(MyModel, wishbone.TargetModel):
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def __init__(self):
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self.prng = Random(763627)
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def can_ack(self, bus):
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# Simulate variable latency.
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return self.prng.randrange(0, 2)
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class MyModelASMI(MyModel, asmibus.TargetModel):
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pass
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def test_wishbone():
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print("*** Wishbone test")
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# The "wishbone.Initiator" library component runs our generator
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# and manipulates the bus signals accordingly.
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master = wishbone.Initiator(my_generator())
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# The "wishbone.Target" library component examines the bus signals
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# and calls into our model object.
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slave = wishbone.Target(MyModelWB())
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# The "wishbone.Tap" library component examines the bus at the slave port
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# and displays the transactions on the console (<TRead...>/<TWrite...>).
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tap = wishbone.Tap(slave.bus)
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# Connect the master to the slave.
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intercon = wishbone.InterconnectPointToPoint(master.bus, slave.bus)
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# A small extra simulation function to terminate the process when
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# the initiator is done (i.e. our generator is exhausted).
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def end_simulation(s):
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s.interrupt = master.done
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fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
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sim = Simulator(fragment)
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sim.run()
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def test_asmi():
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print("*** ASMI test")
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# Create a hub with one port for our initiator.
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hub = asmibus.Hub(32, 32)
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port = hub.get_port()
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hub.finalize()
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# Create the initiator, target and tap (similar to the Wishbone case).
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master = asmibus.Initiator(my_generator(), port)
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slave = asmibus.Target(MyModelASMI(), hub)
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tap = asmibus.Tap(hub)
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# Run the simulation (same as the Wishbone case).
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def end_simulation(s):
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s.interrupt = master.done
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fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
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sim = Simulator(fragment)
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sim.run()
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test_wishbone()
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test_asmi()
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# Output:
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# <TWrite adr:0x0 dat:0x0>
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# Wrote in 0 cycle(s)
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# <TWrite adr:0x1 dat:0x2>
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# Wrote in 0 cycle(s)
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# <TWrite adr:0x2 dat:0x4>
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# Wrote in 0 cycle(s)
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# <TWrite adr:0x3 dat:0x6>
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# Wrote in 1 cycle(s)
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# <TWrite adr:0x4 dat:0x8>
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# Wrote in 1 cycle(s)
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# <TWrite adr:0x5 dat:0xa>
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# Wrote in 2 cycle(s)
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# ...
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# <TRead adr:0x0 dat:0x4>
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# Read 4 in 2 cycle(s)
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# <TRead adr:0x1 dat:0x5>
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# Read 5 in 2 cycle(s)
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# <TRead adr:0x2 dat:0x6>
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# Read 6 in 1 cycle(s)
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# <TRead adr:0x3 dat:0x7>
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# Read 7 in 1 cycle(s)
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# ...
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@ -0,0 +1,89 @@
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from random import Random
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from migen.fhdl.std import *
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from migen.bus.transactions import *
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from migen.bus import wishbone
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from migen.sim.generic import Simulator
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# Our bus master.
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# Python generators let us program bus transactions in an elegant sequential style.
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def my_generator():
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prng = Random(92837)
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# Write to the first addresses.
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for x in range(10):
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t = TWrite(x, 2*x)
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yield t
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print("Wrote in " + str(t.latency) + " cycle(s)")
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# Insert some dead cycles to simulate bus inactivity.
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for delay in range(prng.randrange(0, 3)):
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yield None
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# Read from the first addresses.
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for x in range(10):
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t = TRead(x)
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yield t
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print("Read " + str(t.data) + " in " + str(t.latency) + " cycle(s)")
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for delay in range(prng.randrange(0, 3)):
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yield None
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# Our bus slave.
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class MyModelWB(wishbone.TargetModel):
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def __init__(self):
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self.prng = Random(763627)
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def read(self, address):
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return address + 4
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def can_ack(self, bus):
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# Simulate variable latency.
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return self.prng.randrange(0, 2)
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class TB(Module):
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def __init__(self):
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# The "wishbone.Initiator" library component runs our generator
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# and manipulates the bus signals accordingly.
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self.submodules.master = wishbone.Initiator(my_generator())
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# The "wishbone.Target" library component examines the bus signals
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# and calls into our model object.
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self.submodules.slave = wishbone.Target(MyModelWB())
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# The "wishbone.Tap" library component examines the bus at the slave port
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# and displays the transactions on the console (<TRead...>/<TWrite...>).
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self.submodules.tap = wishbone.Tap(self.slave.bus)
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# Connect the master to the slave.
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self.submodules.intercon = wishbone.InterconnectPointToPoint(self.master.bus, self.slave.bus)
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def do_simulation(self, s):
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# Terminate the simulation when the initiator is done (i.e. our generator is exhausted).
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s.interrupt = self.master.done
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def main():
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tb = TB()
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sim = Simulator(tb)
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sim.run()
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main()
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# Output:
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# <TWrite adr:0x0 dat:0x0>
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# Wrote in 0 cycle(s)
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# <TWrite adr:0x1 dat:0x2>
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# Wrote in 0 cycle(s)
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# <TWrite adr:0x2 dat:0x4>
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# Wrote in 0 cycle(s)
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# <TWrite adr:0x3 dat:0x6>
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# Wrote in 1 cycle(s)
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# <TWrite adr:0x4 dat:0x8>
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# Wrote in 1 cycle(s)
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# <TWrite adr:0x5 dat:0xa>
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# Wrote in 2 cycle(s)
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# ...
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# <TRead adr:0x0 dat:0x4>
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# Read 4 in 2 cycle(s)
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# <TRead adr:0x1 dat:0x5>
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# Read 5 in 2 cycle(s)
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# <TRead adr:0x2 dat:0x6>
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# Read 6 in 1 cycle(s)
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# <TRead adr:0x3 dat:0x7>
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# Read 7 in 1 cycle(s)
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# ...
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