bus: replace simple bus module with new bidirectional Record
This commit is contained in:
Sebastien Bourdeauducq
parent
6a3c413717
commit
29b468529f
103
migen/bus/csr.py
103
migen/bus/csr.py
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@ -1,23 +1,24 @@
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from migen.fhdl.structure import *
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from migen.fhdl.specials import Memory
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from migen.fhdl.module import Module
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from migen.bus.simple import *
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from migen.bus.transactions import *
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from migen.bank.description import CSRStorage
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from migen.genlib.record import *
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from migen.genlib.misc import chooser
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data_width = 8
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class Interface(SimpleInterface):
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class Interface(Record):
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def __init__(self):
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SimpleInterface.__init__(self, Description(
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(M_TO_S, "adr", 14),
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(M_TO_S, "we", 1),
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(M_TO_S, "dat_w", data_width),
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(S_TO_M, "dat_r", data_width)))
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Record.__init__(self, [
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("adr", 14, DIR_M_TO_S),
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("we", 1, DIR_M_TO_S),
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("dat_w", data_width, DIR_M_TO_S),
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("dat_r", data_width, DIR_S_TO_M)])
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class Interconnect(SimpleInterconnect):
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pass
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class Interconnect(Module):
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def __init__(self, master, slaves):
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self.comb += master.connect(*slaves)
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class Initiator(Module):
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def __init__(self, generator, bus=None):
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@ -53,80 +54,74 @@ def _compute_page_bits(nwords):
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else:
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return 0
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class SRAM:
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class SRAM(Module):
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def __init__(self, mem_or_size, address, read_only=None, bus=None):
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if isinstance(mem_or_size, Memory):
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self.mem = mem_or_size
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mem = mem_or_size
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else:
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self.mem = Memory(data_width, mem_or_size//(data_width//8))
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self.address = address
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if self.mem.width > data_width:
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self.csrw_per_memw = (self.mem.width + data_width - 1)//data_width
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self.word_bits = bits_for(self.csrw_per_memw-1)
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mem = Memory(data_width, mem_or_size//(data_width//8))
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if mem.width > data_width:
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csrw_per_memw = (self.mem.width + data_width - 1)//data_width
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word_bits = bits_for(csrw_per_memw-1)
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else:
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self.csrw_per_memw = 1
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self.word_bits = 0
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page_bits = _compute_page_bits(self.mem.depth + self.word_bits)
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csrw_per_memw = 1
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word_bits = 0
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page_bits = _compute_page_bits(mem.depth + word_bits)
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if page_bits:
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self._page = CSRStorage(page_bits, name=self.mem.name_override + "_page")
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else:
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self._page = None
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if read_only is None:
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if hasattr(self.mem, "bus_read_only"):
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read_only = self.mem.bus_read_only
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if hasattr(mem, "bus_read_only"):
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read_only = mem.bus_read_only
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else:
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read_only = False
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self.read_only = read_only
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if bus is None:
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bus = Interface()
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self.bus = bus
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def get_csrs(self):
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if self._page is None:
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return []
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else:
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return [self._page]
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def get_fragment(self):
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port = self.mem.get_port(write_capable=not self.read_only,
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we_granularity=data_width if not self.read_only and self.word_bits else 0)
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###
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self.specials += mem
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port = mem.get_port(write_capable=not read_only,
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we_granularity=data_width if not read_only and word_bits else 0)
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sel = Signal()
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sel_r = Signal()
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sync = [sel_r.eq(sel)]
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comb = [sel.eq(self.bus.adr[9:] == self.address)]
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self.sync += sel_r.eq(sel)
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self.comb += sel.eq(self.bus.adr[9:] == address)
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if self.word_bits:
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word_index = Signal(self.word_bits)
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word_expanded = Signal(self.csrw_per_memw*data_width)
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sync.append(word_index.eq(self.bus.adr[:self.word_bits]))
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comb += [
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if word_bits:
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word_index = Signal(word_bits)
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word_expanded = Signal(csrw_per_memw*data_width)
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sync.append(word_index.eq(self.bus.adr[:word_bits]))
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self.comb += [
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word_expanded.eq(port.dat_r),
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If(sel_r,
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chooser(word_expanded, word_index, self.bus.dat_r, n=self.csrw_per_memw, reverse=True)
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chooser(word_expanded, word_index, self.bus.dat_r, n=csrw_per_memw, reverse=True)
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)
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]
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if not self.read_only:
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comb += [
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If(sel & self.bus.we, port.we.eq((1 << self.word_bits) >> self.bus.adr[:self.word_bits])),
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port.dat_w.eq(Replicate(self.bus.dat_w, self.csrw_per_memw))
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if not read_only:
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self.comb += [
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If(sel & self.bus.we, port.we.eq((1 << word_bits) >> self.bus.adr[:self.word_bits])),
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port.dat_w.eq(Replicate(self.bus.dat_w, csrw_per_memw))
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]
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else:
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comb += [
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If(sel_r,
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self.bus.dat_r.eq(port.dat_r)
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)
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]
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if not self.read_only:
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comb += [
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self.comb += If(sel_r, self.bus.dat_r.eq(port.dat_r))
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if not read_only:
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self.comb += [
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port.we.eq(sel & self.bus.we),
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port.dat_w.eq(self.bus.dat_w)
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]
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if self._page is None:
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comb.append(port.adr.eq(self.bus.adr[self.word_bits:len(port.adr)]))
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self.comb += port.adr.eq(self.bus.adr[word_bits:len(port.adr)])
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else:
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pv = self._page.storage
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comb.append(port.adr.eq(Cat(self.bus.adr[self.word_bits:len(port.adr)-len(pv)], pv)))
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return Fragment(comb, sync, specials={self.mem})
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self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:len(port.adr)-len(pv)], pv))
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def get_csrs(self):
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if self._page is None:
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return []
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else:
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return [self._page]
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@ -1,29 +1,31 @@
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from migen.fhdl.structure import *
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from migen.bus.simple import *
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from migen.fhdl.module import Module
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from migen.genlib.record import *
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def phase_description(a, ba, d):
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return Description(
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(M_TO_S, "address", a),
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(M_TO_S, "bank", ba),
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(M_TO_S, "cas_n", 1),
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(M_TO_S, "cke", 1),
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(M_TO_S, "cs_n", 1),
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(M_TO_S, "ras_n", 1),
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(M_TO_S, "we_n", 1),
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return [
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("address", a, DIR_M_TO_S),
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("bank", ba, DIR_M_TO_S),
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("cas_n", 1, DIR_M_TO_S),
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("cke", 1, DIR_M_TO_S),
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("cs_n", 1, DIR_M_TO_S),
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("ras_n", 1, DIR_M_TO_S),
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("we_n", 1, DIR_M_TO_S),
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(M_TO_S, "wrdata", d),
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(M_TO_S, "wrdata_en", 1),
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(M_TO_S, "wrdata_mask", d//8),
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("wrdata", d, DIR_M_TO_S),
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("wrdata_en", 1, DIR_M_TO_S),
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("wrdata_mask", d//8, DIR_M_TO_S),
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(M_TO_S, "rddata_en", 1),
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(S_TO_M, "rddata", d),
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(S_TO_M, "rddata_valid", 1)
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)
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("rddata_en", 1, DIR_M_TO_S),
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("rddata", d, DIR_S_TO_M),
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("rddata_valid", 1, DIR_S_TO_M)
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]
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class Interface:
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class Interface(Record):
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def __init__(self, a, ba, d, nphases=1):
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self.pdesc = phase_description(a, ba, d)
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self.phases = [SimpleInterface(self.pdesc) for i in range(nphases)]
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layout = [("p"+str(i), phase_description(a, ba, d)) for i in range(nphases)]
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Record.__init__(self, layout)
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self.phases = [getattr(self, "p"+str(i)) for i in range(nphases)]
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for p in self.phases:
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p.cas_n.reset = 1
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p.cs_n.reset = 1
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@ -35,28 +37,18 @@ class Interface:
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r = []
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add_suffix = len(self.phases) > 1
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for n, phase in enumerate(self.phases):
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for signal in self.pdesc.desc:
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if (m2s and signal[0] == M_TO_S) or (s2m and signal[0] == S_TO_M):
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for field, size, direction in phase.layout:
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if (m2s and direction == DIR_M_TO_S) or (s2m and direction == DIR_S_TO_M):
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if add_suffix:
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if signal[0] == M_TO_S:
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if direction == DIR_M_TO_S:
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suffix = "_p" + str(n)
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else:
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suffix = "_w" + str(n)
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else:
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suffix = ""
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r.append(("dfi_" + signal[1] + suffix, getattr(phase, signal[1])))
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r.append(("dfi_" + field + suffix, getattr(phase, field)))
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return r
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def interconnect_stmts(master, slave):
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r = []
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for pm, ps in zip(master.phases, slave.phases):
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r += simple_interconnect_stmts(master.pdesc, pm, [ps])
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return r
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class Interconnect:
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class Interconnect(Module):
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def __init__(self, master, slave):
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self.master = master
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self.slave = slave
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def get_fragment(self):
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return Fragment(interconnect_stmts(self.master, self.slave))
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self.comb += master.connect(slave)
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@ -1,47 +0,0 @@
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from migen.fhdl.structure import *
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from migen.genlib.misc import optree
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(S_TO_M, M_TO_S) = range(2)
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# desc is a list of tuples, each made up of:
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# 0) S_TO_M/M_TO_S: data direction
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# 1) string: name
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# 2) int: width
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class Description:
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def __init__(self, *desc):
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self.desc = desc
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def get_names(self, direction, *exclude_list):
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exclude = set(exclude_list)
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return [signal[1]
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for signal in self.desc
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if signal[0] == direction and signal[1] not in exclude]
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class SimpleInterface:
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def __init__(self, desc):
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self.desc = desc
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modules = self.__module__.split(".")
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busname = modules[len(modules)-1]
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for signal in self.desc.desc:
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signame = signal[1]
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setattr(self, signame, Signal(signal[2], busname + "_" + signame))
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def simple_interconnect_stmts(desc, master, slaves):
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s2m = desc.get_names(S_TO_M)
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m2s = desc.get_names(M_TO_S)
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sl = [getattr(slave, name).eq(getattr(master, name))
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for name in m2s for slave in slaves]
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sl += [getattr(master, name).eq(
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optree("|", [getattr(slave, name) for slave in slaves])
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)
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for name in s2m]
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return sl
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class SimpleInterconnect:
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def __init__(self, master, slaves):
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self.master = master
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self.slaves = slaves
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def get_fragment(self):
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return Fragment(simple_interconnect_stmts(self.master.desc, self.master, self.slaves))
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@ -2,64 +2,59 @@ from migen.fhdl.structure import *
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from migen.fhdl.specials import Memory
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from migen.fhdl.module import Module
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from migen.genlib import roundrobin
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from migen.genlib.record import *
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from migen.genlib.misc import optree
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from migen.bus.simple import *
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from migen.bus.transactions import *
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from migen.sim.generic import Proxy
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_desc = Description(
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(M_TO_S, "adr", 30),
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(M_TO_S, "dat_w", 32),
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(S_TO_M, "dat_r", 32),
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(M_TO_S, "sel", 4),
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(M_TO_S, "cyc", 1),
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(M_TO_S, "stb", 1),
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(S_TO_M, "ack", 1),
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(M_TO_S, "we", 1),
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(M_TO_S, "cti", 3),
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(M_TO_S, "bte", 2),
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(S_TO_M, "err", 1)
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)
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_layout = [
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("adr", 30, DIR_M_TO_S),
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("dat_w", 32, DIR_M_TO_S),
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("dat_r", 32, DIR_S_TO_M),
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("sel", 4, DIR_M_TO_S),
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("cyc", 1, DIR_M_TO_S),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M),
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("we", 1, DIR_M_TO_S),
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("cti", 3, DIR_M_TO_S),
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("bte", 2, DIR_M_TO_S),
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("err", 1, DIR_S_TO_M)
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]
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class Interface(SimpleInterface):
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class Interface(Record):
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def __init__(self):
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SimpleInterface.__init__(self, _desc)
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Record.__init__(self, _layout)
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class InterconnectPointToPoint(SimpleInterconnect):
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class InterconnectPointToPoint(Module):
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def __init__(self, master, slave):
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SimpleInterconnect.__init__(self, master, [slave])
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self.comb += master.connect(slave)
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class Arbiter:
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class Arbiter(Module):
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def __init__(self, masters, target):
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self.masters = masters
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self.target = target
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self.rr = roundrobin.RoundRobin(len(self.masters))
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def get_fragment(self):
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comb = []
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self.submodules.rr = roundrobin.RoundRobin(len(masters))
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# mux master->slave signals
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for name in _desc.get_names(M_TO_S):
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choices = Array(getattr(m, name) for m in self.masters)
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comb.append(getattr(self.target, name).eq(choices[self.rr.grant]))
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for name, size, direction in _layout:
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if direction == DIR_M_TO_S:
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choices = Array(getattr(m, name) for m in masters)
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self.comb += getattr(target, name).eq(choices[self.rr.grant])
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# connect slave->master signals
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for name in _desc.get_names(S_TO_M):
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source = getattr(self.target, name)
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for i, m in enumerate(self.masters):
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dest = getattr(m, name)
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if name == "ack" or name == "err":
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comb.append(dest.eq(source & (self.rr.grant == i)))
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else:
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comb.append(dest.eq(source))
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for name, size, direction in _layout:
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if direction == DIR_S_TO_M:
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source = getattr(target, name)
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for i, m in enumerate(masters):
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dest = getattr(m, name)
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if name == "ack" or name == "err":
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self.comb += dest.eq(source & (self.rr.grant == i))
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else:
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self.comb += dest.eq(source)
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# connect bus requests to round-robin selector
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reqs = [m.cyc for m in self.masters]
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comb.append(self.rr.request.eq(Cat(*reqs)))
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return Fragment(comb) + self.rr.get_fragment()
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reqs = [m.cyc for m in masters]
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self.comb += self.rr.request.eq(Cat(*reqs))
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class Decoder:
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class Decoder(Module):
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# slaves is a list of pairs:
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# 0) function that takes the address signal and returns a FHDL expression
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# that evaluates to 1 when the slave is selected and 0 otherwise.
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@ -67,55 +62,43 @@ class Decoder:
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# register adds flip-flops after the address comparators. Improves timing,
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# but breaks Wishbone combinatorial feedback.
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def __init__(self, master, slaves, register=False):
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self.master = master
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self.slaves = slaves
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self.register = register
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def get_fragment(self):
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comb = []
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sync = []
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ns = len(self.slaves)
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ns = len(slaves)
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slave_sel = Signal(ns)
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slave_sel_r = Signal(ns)
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# decode slave addresses
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comb += [slave_sel[i].eq(fun(self.master.adr))
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for i, (fun, bus) in enumerate(self.slaves)]
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if self.register:
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sync.append(slave_sel_r.eq(slave_sel))
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self.comb += [slave_sel[i].eq(fun(master.adr))
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for i, (fun, bus) in enumerate(slaves)]
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if register:
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self.sync += slave_sel_r.eq(slave_sel)
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else:
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comb.append(slave_sel_r.eq(slave_sel))
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self.comb += slave_sel_r.eq(slave_sel)
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# connect master->slaves signals except cyc
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m2s_names = _desc.get_names(M_TO_S, "cyc")
|
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comb += [getattr(slave[1], name).eq(getattr(self.master, name))
|
||||
for name in m2s_names for slave in self.slaves]
|
||||
for slave in slaves:
|
||||
for name, size, direction in _layout:
|
||||
if direction == DIR_M_TO_S and name != "cyc":
|
||||
self.comb += getattr(slave[1], name).eq(getattr(master, name))
|
||||
|
||||
# combine cyc with slave selection signals
|
||||
comb += [slave[1].cyc.eq(self.master.cyc & slave_sel[i])
|
||||
for i, slave in enumerate(self.slaves)]
|
||||
self.comb += [slave[1].cyc.eq(master.cyc & slave_sel[i])
|
||||
for i, slave in enumerate(slaves)]
|
||||
|
||||
# generate master ack (resp. err) by ORing all slave acks (resp. errs)
|
||||
comb += [
|
||||
self.master.ack.eq(optree("|", [slave[1].ack for slave in self.slaves])),
|
||||
self.master.err.eq(optree("|", [slave[1].err for slave in self.slaves]))
|
||||
self.comb += [
|
||||
master.ack.eq(optree("|", [slave[1].ack for slave in slaves])),
|
||||
master.err.eq(optree("|", [slave[1].err for slave in slaves]))
|
||||
]
|
||||
|
||||
# mux (1-hot) slave data return
|
||||
masked = [Replicate(slave_sel_r[i], len(self.master.dat_r)) & self.slaves[i][1].dat_r for i in range(len(self.slaves))]
|
||||
comb.append(self.master.dat_r.eq(optree("|", masked)))
|
||||
|
||||
return Fragment(comb, sync)
|
||||
masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
|
||||
self.comb += master.dat_r.eq(optree("|", masked))
|
||||
|
||||
class InterconnectShared:
|
||||
class InterconnectShared(Module):
|
||||
def __init__(self, masters, slaves, register=False):
|
||||
self._shared = Interface()
|
||||
self._arbiter = Arbiter(masters, self._shared)
|
||||
self._decoder = Decoder(self._shared, slaves, register)
|
||||
|
||||
def get_fragment(self):
|
||||
return self._arbiter.get_fragment() + self._decoder.get_fragment()
|
||||
shared = Interface()
|
||||
self.submodules += Arbiter(masters, shared)
|
||||
self.submodules += Decoder(shared, slaves, register)
|
||||
|
||||
class Tap(Module):
|
||||
def __init__(self, bus, handler=print):
|
||||
|
|
@ -200,34 +183,33 @@ class Target(Module):
|
|||
else:
|
||||
bus.ack = 0
|
||||
|
||||
class SRAM:
|
||||
class SRAM(Module):
|
||||
def __init__(self, mem_or_size, bus=None):
|
||||
if isinstance(mem_or_size, Memory):
|
||||
assert(mem_or_size.width <= 32)
|
||||
self.mem = mem_or_size
|
||||
mem = mem_or_size
|
||||
else:
|
||||
self.mem = Memory(32, mem_or_size//4)
|
||||
mem = Memory(32, mem_or_size//4)
|
||||
if bus is None:
|
||||
bus = Interface()
|
||||
self.bus = bus
|
||||
|
||||
def get_fragment(self):
|
||||
###
|
||||
|
||||
# memory
|
||||
port = self.mem.get_port(write_capable=True, we_granularity=8)
|
||||
self.specials += mem
|
||||
port = mem.get_port(write_capable=True, we_granularity=8)
|
||||
# generate write enable signal
|
||||
comb = [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
|
||||
self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
|
||||
for i in range(4)]
|
||||
# address and data
|
||||
comb += [
|
||||
self.comb += [
|
||||
port.adr.eq(self.bus.adr[:len(port.adr)]),
|
||||
port.dat_w.eq(self.bus.dat_w),
|
||||
self.bus.dat_r.eq(port.dat_r)
|
||||
]
|
||||
# generate ack
|
||||
sync = [
|
||||
self.sync += [
|
||||
self.bus.ack.eq(0),
|
||||
If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
|
||||
self.bus.ack.eq(1)
|
||||
)
|
||||
If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
|
||||
]
|
||||
return Fragment(comb, sync, specials={self.mem})
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ from migen.fhdl.specials import Memory
|
|||
from migen.bus import wishbone
|
||||
from migen.genlib.fsm import FSM
|
||||
from migen.genlib.misc import split, displacer, chooser
|
||||
from migen.genlib.record import Record
|
||||
from migen.genlib.record import Record, layout_len
|
||||
|
||||
# cachesize (in 32-bit words) is the size of the data store, must be a power of 2
|
||||
class WB2ASMI:
|
||||
|
|
@ -60,15 +60,14 @@ class WB2ASMI:
|
|||
]
|
||||
|
||||
# Tag memory
|
||||
tag_mem = Memory(tagbits+1, 2**linebits)
|
||||
tag_port = tag_mem.get_port(write_capable=True)
|
||||
|
||||
tag_layout = [("tag", tagbits), ("dirty", 1)]
|
||||
tag_mem = Memory(layout_len(tag_layout), 2**linebits)
|
||||
tag_port = tag_mem.get_port(write_capable=True)
|
||||
tag_do = Record(tag_layout)
|
||||
tag_di = Record(tag_layout)
|
||||
comb += [
|
||||
Cat(*tag_do.flatten()).eq(tag_port.dat_r),
|
||||
tag_port.dat_w.eq(Cat(*tag_di.flatten()))
|
||||
tag_do.raw_bits().eq(tag_port.dat_r),
|
||||
tag_port.dat_w.eq(tag_di.raw_bits())
|
||||
]
|
||||
|
||||
comb += [
|
||||
|
|
|
|||
Loading…
Reference in New Issue