interconnect/wishbone: fix Converter case when buses are identical

2019-10-11 21:49:11 +02:00 · 2019-10-11 21:49:11 +02:00 · 29e51f5e97
parent ae9c25b74f
commit 29e51f5e97
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@ -486,7 +486,7 @@ class Converter(Module):
            upconverter = UpConverter(master, slave)
            self.submodules += upconverter
        else:
-            master.connect(slave)
+            self.comb += master.connect(slave)


 class Cache(Module):