interconnect/wishbone: fix Converter case when buses are identical
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@ -486,7 +486,7 @@ class Converter(Module):
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upconverter = UpConverter(master, slave)
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upconverter = UpConverter(master, slave)
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self.submodules += upconverter
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self.submodules += upconverter
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else:
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else:
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master.connect(slave)
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self.comb += master.connect(slave)
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class Cache(Module):
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class Cache(Module):
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