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soc: simplify/fix csr busword

This commit is contained in:
Sebastien Bourdeauducq 2015-04-01 15:48:56 +08:00
parent 04f29e97e2
commit 2a1112b912
1 changed files with 2 additions and 2 deletions
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4
misoclib/soc/__init__.py
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@ -177,9 +177,9 @@ class SoC(Module):
data_width=self.csr_data_width, address_width=self.csr_address_width) data_width=self.csr_data_width, address_width=self.csr_address_width)
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks: for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs) self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams: for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory) self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, memory)
# Interrupts # Interrupts
if hasattr(self.cpu_or_bridge, "interrupt"): if hasattr(self.cpu_or_bridge, "interrupt"):