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fhdl: phase out pads

This commit is contained in:
Sebastien Bourdeauducq 2012-04-02 19:21:43 +02:00
parent 1b60c7ff40
commit 2a4e49e381
3 changed files with 1 additions and 5 deletions
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1
doc/index.rst
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@ -233,7 +233,6 @@ A "fragment" is a unit of logic, which is composed of:
* a list of synchronous statements. * a list of synchronous statements.
* a list of instances. * a list of instances.
* a list of memories. * a list of memories.
* a set of pads, which are signals intended to be connected to off-chip devices.
* a list of simulation functions (see :ref:`simulating`). * a list of simulation functions (see :ref:`simulating`).
Fragments can reference arbitrary signals, including signals that are referenced in other fragments. Fragments can be combined using the "+" operator, which returns a new fragment containing the concatenation of each pair of lists. Fragments can reference arbitrary signals, including signals that are referenced in other fragments. Fragments can be combined using the "+" operator, which returns a new fragment containing the concatenation of each pair of lists.

4
migen/fhdl/structure.py
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@ -268,7 +268,7 @@ class Memory:
self.init = init self.init = init
class Fragment: class Fragment:
def __init__(self, comb=None, sync=None, instances=None, memories=None, pads=set(), sim=None): def __init__(self, comb=None, sync=None, instances=None, memories=None, sim=None):
if comb is None: comb = [] if comb is None: comb = []
if sync is None: sync = [] if sync is None: sync = []
if instances is None: instances = [] if instances is None: instances = []
@ -278,7 +278,6 @@ class Fragment:
self.sync = _sl(sync) self.sync = _sl(sync)
self.instances = instances self.instances = instances
self.memories = memories self.memories = memories
self.pads = pads
self.sim = sim self.sim = sim
def __add__(self, other): def __add__(self, other):
@ -286,7 +285,6 @@ class Fragment:
self.sync.l + other.sync.l, self.sync.l + other.sync.l,
self.instances + other.instances, self.instances + other.instances,
self.memories + other.memories, self.memories + other.memories,
self.pads | other.pads,
self.sim + other.sim) self.sim + other.sim)
def call_sim(self, simulator): def call_sim(self, simulator):

1
migen/fhdl/verilog.py
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@ -244,7 +244,6 @@ def convert(f, ios=set(), name="top",
if rst_signal is None: if rst_signal is None:
rst_signal = Signal(name_override="sys_rst") rst_signal = Signal(name_override="sys_rst")
ios.add(rst_signal) ios.add(rst_signal)
ios |= f.pads
ns = build_namespace(list_signals(f) \ ns = build_namespace(list_signals(f) \
| list_inst_ios(f, True, True, True) \ | list_inst_ios(f, True, True, True) \