cores/dma: Automatically call add_ctrl method in add_csr is ctrl are not present.
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9c07b45f3c
commit
2a83bce63e
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@ -71,7 +71,6 @@ class WishboneDMAReader(LiteXModule):
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# CSRs.
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# CSRs.
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if with_csr:
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if with_csr:
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self.add_ctrl()
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self.add_csr()
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self.add_csr()
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def add_ctrl(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
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def add_ctrl(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
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@ -117,6 +116,8 @@ class WishboneDMAReader(LiteXModule):
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fsm.act("DONE", self.done.eq(1))
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fsm.act("DONE", self.done.eq(1))
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def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
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def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
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if not hasattr(self, "base"):
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self.add_ctrl()
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self._base = CSRStorage(64, reset=default_base)
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self._base = CSRStorage(64, reset=default_base)
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self._length = CSRStorage(32, reset=default_length)
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self._length = CSRStorage(32, reset=default_length)
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self._enable = CSRStorage(reset=default_enable)
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self._enable = CSRStorage(reset=default_enable)
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@ -173,7 +174,6 @@ class WishboneDMAWriter(LiteXModule):
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# CSRs.
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# CSRs.
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if with_csr:
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if with_csr:
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self.add_ctrl()
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self.add_csr()
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self.add_csr()
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def add_ctrl(self, default_base=0, default_length=0, default_enable=0, default_loop=0, ready_on_idle=1):
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def add_ctrl(self, default_base=0, default_length=0, default_enable=0, default_loop=0, ready_on_idle=1):
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@ -225,6 +225,8 @@ class WishboneDMAWriter(LiteXModule):
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fsm.act("DONE", self.done.eq(1))
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fsm.act("DONE", self.done.eq(1))
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def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
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def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
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if not hasattr(self, "base"):
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self.add_ctrl()
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self._base = CSRStorage(64, reset=default_base)
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self._base = CSRStorage(64, reset=default_base)
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self._length = CSRStorage(32, reset=default_length)
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self._length = CSRStorage(32, reset=default_length)
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self._enable = CSRStorage(reset=default_enable)
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self._enable = CSRStorage(reset=default_enable)
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