soc/integration/soc_core: add ident_version parameter to allow adding soc version to identifier
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@ -10,6 +10,17 @@ from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
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__all__ = ["mem_decoder", "SoCCore", "soc_core_args", "soc_core_argdict"]
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__all__ = ["mem_decoder", "SoCCore", "soc_core_args", "soc_core_argdict"]
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def version(with_time=True):
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import datetime
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import time
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if with_time:
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return datetime.datetime.fromtimestamp(
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time.time()).strftime("%Y-%m-%d %H:%M:%S")
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else:
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return datetime.datetime.fromtimestamp(
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time.time()).strftime("%Y-%m-%d")
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def mem_decoder(address, start=26, end=29):
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def mem_decoder(address, start=26, end=29):
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return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
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return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
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@ -42,7 +53,7 @@ class SoCCore(Module):
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shadow_base=0x80000000,
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shadow_base=0x80000000,
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csr_data_width=8, csr_address_width=14,
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csr_data_width=8, csr_address_width=14,
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with_uart=True, uart_baudrate=115200, uart_stub=False,
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with_uart=True, uart_baudrate=115200, uart_stub=False,
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ident="",
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ident="", ident_version=False,
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with_timer=True):
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with_timer=True):
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self.config = dict()
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self.config = dict()
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@ -114,6 +125,8 @@ class SoCCore(Module):
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self.submodules.uart = uart.UART(self.uart_phy)
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self.submodules.uart = uart.UART(self.uart_phy)
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if ident:
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if ident:
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if ident_version:
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ident = ident + " " + version()
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self.submodules.identifier = identifier.Identifier(ident)
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self.submodules.identifier = identifier.Identifier(ident)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
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self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
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