soc/cores/cpu/vexriscv: update submodule

2018-12-12 09:38:53 +01:00 · 2018-12-12 09:38:53 +01:00 · 2ace45e6f8
parent 6d6c2b4c45
commit 2ace45e6f8
2 changed files with 3 additions and 3 deletions
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@ -1 +1 @@
-Subproject commit 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5
+Subproject commit d7bbc2c167f1a0886c446d3c305d0ed4388570be
--- a/litex/soc/software/include/base/csr-defs.h
+++ b/litex/soc/software/include/base/csr-defs.h
@ -3,8 +3,8 @@

 #define CSR_MSTATUS_MIE 0x8

-#define CSR_IRQ_MASK 0x330
-#define CSR_IRQ_PENDING 0x360
+#define CSR_IRQ_MASK 0xBC0
+#define CSR_IRQ_PENDING 0xFC0

 #define CSR_DCACHE_INFO 0xCC0