Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

Use common definition for FinalizeError

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2013-03-09 19:03:13 +01:00
parent b75fb7f97c
commit 2b8dc52c13
3 changed files with 3 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
migen/bus/asmibus.py
View file

@ -3,9 +3,6 @@ from migen.genlib.misc import optree
from migen.bus.transactions import * from migen.bus.transactions import *
from migen.sim.generic import Proxy, PureSimulable from migen.sim.generic import Proxy, PureSimulable
class FinalizeError(Exception):
pass
(SLOT_EMPTY, SLOT_PENDING, SLOT_PROCESSING) = range(3) (SLOT_EMPTY, SLOT_PENDING, SLOT_PROCESSING) = range(3)
class Slot: class Slot:

3
migen/fhdl/structure.py
View file

@ -276,3 +276,6 @@ class ClockDomain:
n_rst = n2 n_rst = n2
self.clk = Signal(name_override=n_clk) self.clk = Signal(name_override=n_clk)
self.rst = Signal(name_override=n_rst) self.rst = Signal(name_override=n_rst)
class FinalizeError(Exception):
pass

3
migen/pytholite/reg.py
View file

@ -3,9 +3,6 @@ from operator import itemgetter
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.fhdl import visit as fhdl from migen.fhdl import visit as fhdl
class FinalizeError(Exception):
pass
class AbstractLoad: class AbstractLoad:
def __init__(self, target, source): def __init__(self, target, source):
self.target = target self.target = target