add verilog backend to use the core with a "standard" flow

litesata/phy/__init__.py

@@ -4,6 +4,7 @@ from litesata.phy.datapath import *
 
 class LiteSATAPHY(Module):
 	def __init__(self, device, pads, revision, clk_freq):
+		self.pads = pads
 		self.revision = revision
 		# Transceiver / Clocks
 		if device[:3] == "xc7": # Kintex 7

make.py

@@ -4,7 +4,9 @@ import sys, os, argparse, subprocess, struct, importlib
 
 from mibuild.tools import write_to_file
 from migen.util.misc import autotype
-from migen.fhdl import simplify
+from migen.fhdl import verilog, edif
+from migen.fhdl.structure import _Fragment
+from mibuild import tools
 
 from misoclib.gensoc import cpuif
 
@@ -68,7 +70,7 @@ if __name__ == "__main__":
 	soc.finalize()
 
 	# decode actions
-	action_list = ["clean", "build-csr-csv", "build-rtl", "build-bitstream", "load-bitstream", "all"]
+	action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
 	actions = {k: False for k in action_list}
 	for action in args.action:
 		if action in actions:
@@ -115,9 +117,8 @@ Ports: {}
 		actions["build-bitstream"] = True
 		actions["load-bitstream"] = True
 
-	if actions["build-rtl"]:
+	if actions["build-core"]:
 		actions["clean"] = True
-		actions["build-csr-csv"] = True
 
 	if actions["build-bitstream"]:
 		actions["clean"] = True
@@ -132,8 +133,13 @@ Ports: {}
 		csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
 		write_to_file(args.csr_csv, csr_csv)
 
-	if actions["build-rtl"]:
-		raise NotImplementedError()
+	if actions["build-core"]:
+		ios = soc.get_ios()
+		if not isinstance(soc, _Fragment):
+			soc = soc.get_fragment()
+		platform.finalize(soc)
+		src = verilog.convert(soc, ios)
+		tools.write_to_file("build/litesata.v", src)
 
 	if actions["build-bitstream"]:
 		platform.build(soc, build_name=build_name)

platforms/kc705.py

@@ -43,17 +43,6 @@ _io = [
 
 	("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
 
-	("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
-	("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
-	("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
-	("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
-	("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
-
-	("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
-	("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
-	("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
-	("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
-
 	("clk200", 0,
 		Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
 		Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
@@ -73,7 +62,7 @@ _io = [
 		IOStandard("LVCMOS25")
 	),
 
-	("sata0", 0,
+	("sata", 0,
 		Subsignal("refclk_p", Pins("C8")),
 		Subsignal("refclk_n", Pins("C7")),
 		Subsignal("txp", Pins("D2")),
@@ -94,7 +83,7 @@ def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
 	class RealPlatform(xilinx_platform):
 		bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
 
-		def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
+		def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset")):
 			xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
 
 		def create_programmer(self):

platforms/verilog_backend.py

@@ -0,0 +1,24 @@
+from mibuild.generic_platform import *
+from mibuild.xilinx_common import CRG_DS
+from mibuild.xilinx_vivado import XilinxVivadoPlatform
+
+_io = [
+	("sys_clk", 0, Pins("X")),
+	("sys_rst", 1, Pins("X")),
+
+	("sata", 0,
+		Subsignal("refclk_p", Pins("C8")),
+		Subsignal("refclk_n", Pins("C7")),
+		Subsignal("txp", Pins("D2")),
+		Subsignal("txn", Pins("D1")),
+		Subsignal("rxp", Pins("E4")),
+		Subsignal("rxn", Pins("E3")),
+	),
+]
+
+class Platform(XilinxVivadoPlatform):
+	def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset"), **kwargs):
+		XilinxVivadoPlatform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
+
+	def do_finalize(self, *args, **kwargs):
+		pass

targets/bist.py

@@ -139,7 +139,7 @@ class BISTSoC(GenSoC, AutoCSR):
 		self.crg = _CRG(platform)
 
 		# SATA PHY/Core/Frontend
-		self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata0"), "SATA2", clk_freq)
+		self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq)
 		self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME
 		self.sata = LiteSATA(self.sata_phy, with_crossbar=True, with_bist=True, with_bist_csr=True)
 

targets/core.py

@@ -0,0 +1,63 @@
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litesata.common import *
+from litesata.phy import LiteSATAPHY
+from litesata import LiteSATA
+
+class _CRG(Module):
+	def __init__(self, platform):
+		self.cd_sys = ClockDomain()
+		self.reset = Signal()
+		self.comb += self.cd_sys.clk.eq(platform.request("sys_clk"))
+		self.specials += [
+			AsyncResetSynchronizer(self.cd_sys, platform.request("sys_rst") | self.reset),
+		]
+
+class LiteSATACore(Module):
+	default_platform = "verilog_backend"
+
+	def __init__(self, platform):
+		clk_freq = 166*1000000
+		self.crg = _CRG(platform)
+
+		# SATA PHY/Core/Frontend
+		self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq)
+		self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME
+		self.sata = LiteSATA(self.sata_phy, with_crossbar=True)
+
+		# Get user ports from crossbar
+		n = 4
+		self.crossbar_ports = self.sata.crossbar.get_ports(n)
+
+	def get_ios(self):
+		# clock / reset
+		ios = {self.crg.cd_sys.clk, self.crg.cd_sys.rst}
+
+		# Transceiver
+		for e in dir(self.sata_phy.pads):
+			obj = getattr(self.sata_phy.pads, e)
+			if isinstance(obj, Signal):
+				ios = ios.union({obj})
+
+		# User ports
+		def _iter_layout(layout):
+			for e in layout:
+				if isinstance(e[1], list):
+					yield from _iter_layout(e[1])
+				else:
+					yield e
+
+		sink_layout = command_tx_description(32).get_full_layout()
+		source_layout = command_rx_description(32).get_full_layout()
+
+		for crossbar_port in self.crossbar_ports:
+			for e in _iter_layout(sink_layout):
+					obj = getattr(crossbar_port.source, e[0])
+					ios = ios.union({obj})
+			for e in _iter_layout(source_layout):
+					obj = getattr(crossbar_port.sink, e[0])
+					ios = ios.union({obj})
+		return ios
+
+
+default_subtarget = LiteSATACore