liteeth: more pep8 (when convenient), should be almost OK

misoclib/com/liteeth/common.py

@@ -266,7 +266,11 @@ def eth_etherbone_packet_description(dw):
 
 def eth_etherbone_packet_user_description(dw):
     param_layout = _layout_from_header(etherbone_packet_header)
-    param_layout = _remove_from_layout(param_layout, "magic", "portsize", "addrsize", "version")
+    param_layout = _remove_from_layout(param_layout,
+                                       "magic",
+                                       "portsize",
+                                       "addrsize",
+                                       "version")
     param_layout += eth_udp_user_description(dw).param_layout
     payload_layout = [
         ("data", dw),

misoclib/com/liteeth/core/etherbone/packet.py

@@ -120,7 +120,9 @@ class LiteEthEtherbonePacketRX(Module):
         )
         fsm.act("DROP",
             depacketizer.source.ack.eq(1),
-            If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
+            If(depacketizer.source.stb &
+               depacketizer.source.eop &
+               depacketizer.source.ack,
                 NextState("IDLE")
             )
         )

misoclib/com/liteeth/core/etherbone/record.py

@@ -29,7 +29,8 @@ class LiteEthEtherboneRecordReceiver(Module):
 
         # # #
 
-        fifo = SyncFIFO(eth_etherbone_record_description(32), buffer_depth, buffered=True)
+        fifo = SyncFIFO(eth_etherbone_record_description(32), buffer_depth,
+                        buffered=True)
         self.submodules += fifo
         self.comb += Record.connect(sink, fifo.sink)
 
@@ -179,7 +180,8 @@ class LiteEthEtherboneRecord(Module):
         self.comb += [
             Record.connect(sender.source, packetizer.sink),
             Record.connect(packetizer.source, source),
-            source.length.eq(sender.source.wcount*4 + 4 + etherbone_record_header_len),  # XXX improve this
+            # XXX improve this
+            source.length.eq(sender.source.wcount*4 + 4 + etherbone_record_header_len),
             source.ip_address.eq(last_ip_address)
         ]
         if endianness is "big":

misoclib/com/liteeth/core/icmp/__init__.py

@@ -112,7 +112,9 @@ class LiteEthICMPRX(Module):
         )
         fsm.act("DROP",
             depacketizer.source.ack.eq(1),
-            If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
+            If(depacketizer.source.stb &
+               depacketizer.source.eop &
+               depacketizer.source.ack,
                 NextState("IDLE")
             )
         )

misoclib/com/liteeth/core/ip/__init__.py

@@ -91,7 +91,9 @@ class LiteEthIPTX(Module):
         )
         fsm.act("DROP",
             packetizer.source.ack.eq(1),
-            If(packetizer.source.stb & packetizer.source.eop & packetizer.source.ack,
+            If(packetizer.source.stb &
+               packetizer.source.eop &
+               packetizer.source.ack,
                 NextState("IDLE")
             )
         )
@@ -167,7 +169,9 @@ class LiteEthIPRX(Module):
         )
         fsm.act("DROP",
             depacketizer.source.ack.eq(1),
-            If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
+            If(depacketizer.source.stb &
+               depacketizer.source.eop &
+               depacketizer.source.ack,
                 NextState("IDLE")
             )
         )

misoclib/com/liteeth/core/udp/__init__.py

@@ -112,7 +112,9 @@ class LiteEthUDPRX(Module):
         )
         fsm.act("DROP",
             depacketizer.source.ack.eq(1),
-            If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
+            If(depacketizer.source.stb &
+               depacketizer.source.eop &
+               depacketizer.source.ack,
                 NextState("IDLE")
             )
         )

misoclib/com/liteeth/core/udp/crossbar.py

@@ -33,13 +33,15 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
         user_port = LiteEthUDPUserPort(dw)
         internal_port = LiteEthUDPUserPort(8)
         if dw != 8:
-            converter = Converter(eth_udp_user_description(user_port.dw), eth_udp_user_description(8))
+            converter = Converter(eth_udp_user_description(user_port.dw),
+                                  eth_udp_user_description(8))
             self.submodules += converter
             self.comb += [
                 Record.connect(user_port.sink, converter.sink),
                 Record.connect(converter.source, internal_port.sink)
             ]
-            converter = Converter(eth_udp_user_description(8), eth_udp_user_description(user_port.dw))
+            converter = Converter(eth_udp_user_description(8),
+                                  eth_udp_user_description(user_port.dw))
             self.submodules += converter
             self.comb += [
                 Record.connect(internal_port.source, converter.sink),

misoclib/com/liteeth/example_designs/test/make.py

@@ -8,7 +8,7 @@ def _get_args():
     parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
     parser.add_argument("--port", default="2", help="UART port")
     parser.add_argument("--baudrate", default=115200, help="UART baudrate")
-    parser.add_argument("--ip_address", default="192.168.0.42", help="Etherbone  IP address")
+    parser.add_argument("--ip_address", default="192.168.0.42", help="Etherbone IP address")
     parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port")
     parser.add_argument("--busword", default=32, help="CSR busword")
 

misoclib/com/liteeth/generic/crossbar.py

@@ -23,7 +23,9 @@ class LiteEthCrossbar(Module):
 
         # RX dispatch
         sources = [port.source for port in self.users.values()]
-        self.submodules.dispatcher = Dispatcher(self.master.sink, sources, one_hot=True)
+        self.submodules.dispatcher = Dispatcher(self.master.sink,
+                                                sources,
+                                                one_hot=True)
         cases = {}
         cases["default"] = self.dispatcher.sel.eq(0)
         for i, (k, v) in enumerate(self.users.items()):

misoclib/com/liteeth/mac/core/__init__.py

@@ -68,8 +68,12 @@ class LiteEthMACCore(Module, AutoCSR):
         # Converters
         if dw != phy.dw:
             reverse = endianness == "big"
-            tx_converter = Converter(eth_phy_description(dw), eth_phy_description(phy.dw), reverse=reverse)
+            tx_converter = Converter(eth_phy_description(dw),
-            rx_converter = Converter(eth_phy_description(phy.dw), eth_phy_description(dw), reverse=reverse)
+                                     eth_phy_description(phy.dw),
+                                     reverse=reverse)
+            rx_converter = Converter(eth_phy_description(phy.dw),
+                                     eth_phy_description(dw),
+                                     reverse=reverse)
             self.submodules += RenameClockDomains(tx_converter, "eth_tx")
             self.submodules += RenameClockDomains(rx_converter, "eth_rx")
 

misoclib/com/liteeth/phy/gmii.py

@@ -63,10 +63,10 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
         self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
         # XXX Xilinx specific, replace BUFGMUX with a generic clock buffer?
         self.specials += Instance("BUFGMUX",
-                            i_I0=self.cd_eth_rx.clk,
+                                  i_I0=self.cd_eth_rx.clk,
-                            i_I1=clock_pads.tx,
+                                  i_I1=clock_pads.tx,
-                            i_S=mii_mode,
+                                  i_S=mii_mode,
-                            o_O=self.cd_eth_tx.clk)
+                                  o_O=self.cd_eth_tx.clk)
 
         if with_hw_init_reset:
             reset = Signal()
@@ -89,7 +89,11 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
 class LiteEthPHYGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
-        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
+        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads,
-        self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads), "eth_tx")
+                                                pads,
-        self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads), "eth_rx")
+                                                with_hw_init_reset)
+        self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads),
+                                                "eth_tx")
+        self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads),
+                                                "eth_rx")
         self.sink, self.source = self.tx.sink, self.rx.source

misoclib/com/liteeth/phy/mii.py

@@ -15,7 +15,8 @@ class LiteEthPHYMIITX(Module):
 
         if hasattr(pads, "tx_er"):
             self.sync += pads.tx_er.eq(0)
-        converter = Converter(converter_description(8), converter_description(4))
+        converter = Converter(converter_description(8),
+                              converter_description(4))
         self.submodules += converter
         self.comb += [
             converter.sink.stb.eq(sink.stb),
@@ -42,7 +43,8 @@ class LiteEthPHYMIIRX(Module):
         sop = FlipFlop(reset=1)
         self.submodules += sop
 
-        converter = Converter(converter_description(4), converter_description(8))
+        converter = Converter(converter_description(4),
+                              converter_description(8))
         converter = InsertReset(converter)
         self.submodules += converter
 

misoclib/com/liteeth/test/etherbone_tb.py

@@ -65,7 +65,8 @@ class TB(Module):
             # test writes
             if test_writes:
                 writes_datas = [j for j in range(16)]
-                writes = etherbone.EtherboneWrites(base_addr=0x1000, datas=writes_datas)
+                writes = etherbone.EtherboneWrites(base_addr=0x1000,
+                                                   datas=writes_datas)
                 record = etherbone.EtherboneRecord()
                 record.writes = writes
                 record.reads = None
@@ -88,7 +89,8 @@ class TB(Module):
             # test reads
             if test_reads:
                 reads_addrs = [0x1000 + 4*j for j in range(16)]
-                reads = etherbone.EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
+                reads = etherbone.EtherboneReads(base_ret_addr=0x1000,
+                                                 addrs=reads_addrs)
                 record = etherbone.EtherboneRecord()
                 record.writes = None
                 record.reads = reads

misoclib/com/liteeth/test/model/arp.py

@@ -27,7 +27,9 @@ class ARPPacket(Packet):
     def encode(self):
         header = 0
         for k, v in sorted(arp_header.items()):
-            value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
+            value = merge_bytes(split_bytes(getattr(self, k),
+                                            math.ceil(v.width/8)),
+                                            "little")
             header += (value << v.offset+(v.byte*8))
         for d in split_bytes(header, arp_header_len):
             self.insert(0, d)

misoclib/com/liteeth/test/model/etherbone.py

@@ -194,7 +194,9 @@ class EtherboneRecord(Packet):
             self.set_reads(self.reads)
         header = 0
         for k, v in sorted(etherbone_record_header.items()):
-            value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
+            value = merge_bytes(split_bytes(getattr(self, k),
+                                            math.ceil(v.width/8)),
+                                            "little")
             header += (value << v.offset+(v.byte*8))
         for d in split_bytes(header, etherbone_record_header_len):
             self.insert(0, d)

misoclib/com/liteeth/test/model/icmp.py

@@ -25,7 +25,9 @@ class ICMPPacket(Packet):
     def encode(self):
         header = 0
         for k, v in sorted(icmp_header.items()):
-            value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
+            value = merge_bytes(split_bytes(getattr(self, k),
+                                            math.ceil(v.width/8)),
+                                            "little")
             header += (value << v.offset+(v.byte*8))
         for d in split_bytes(header, icmp_header_len):
             self.insert(0, d)

misoclib/com/liteeth/test/model/ip.py

@@ -44,7 +44,9 @@ class IPPacket(Packet):
     def encode(self):
         header = 0
         for k, v in sorted(ipv4_header.items()):
-            value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
+            value = merge_bytes(split_bytes(getattr(self, k),
+                                            math.ceil(v.width/8)),
+                                            "little")
             header += (value << v.offset+(v.byte*8))
         for d in split_bytes(header, ipv4_header_len):
             self.insert(0, d)

misoclib/com/liteeth/test/model/mac.py

@@ -60,7 +60,9 @@ class MACPacket(Packet):
     def encode_header(self):
         header = 0
         for k, v in sorted(mac_header.items()):
-            value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
+            value = merge_bytes(split_bytes(getattr(self, k),
+                                            math.ceil(v.width/8)),
+                                            "little")
             header += (value << v.offset+(v.byte*8))
         for d in split_bytes(header, mac_header_len):
             self.insert(0, d)

misoclib/com/liteeth/test/model/udp.py

@@ -25,7 +25,9 @@ class UDPPacket(Packet):
     def encode(self):
         header = 0
         for k, v in sorted(udp_header.items()):
-            value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
+            value = merge_bytes(split_bytes(getattr(self, k),
+                                            math.ceil(v.width/8)),
+                                            "little")
             header += (value << v.offset+(v.byte*8))
         for d in split_bytes(header, udp_header_len):
             self.insert(0, d)