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targets: remove sdcard clock domain (now generated in the PHY).

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This commit is contained in:
Florent Kermarrec 2020-07-03 20:11:05 +02:00
parent 31a9273c6d
commit 2bfa372b7c
3 changed files with 0 additions and 7 deletions
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2
litex/boards/targets/nexys4ddr.py
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@ -30,7 +30,6 @@ class _CRG(Module):
self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
self.clock_domains.cd_sd = ClockDomain()
# # #
@ -42,7 +41,6 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 50e6)
pll.create_clkout(self.cd_sd, 10e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)

2
litex/boards/targets/nexys_video.py
View file

@ -30,7 +30,6 @@ class _CRG(Module):
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain()
self.clock_domains.cd_sd = ClockDomain()
# # #
@ -42,7 +41,6 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_clk100, 100e6)
pll.create_clkout(self.cd_sd, 10e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)

3
litex/boards/targets/ulx3s.py
View file

@ -32,7 +32,6 @@ class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
self.clock_domains.cd_sd = ClockDomain()
# # #
@ -46,9 +45,7 @@ class _CRG(Module):
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
pll.create_clkout(self.cd_sd, 10e6)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
self.specials += AsyncResetSynchronizer(self.cd_sd, ~pll.locked | rst)
# USB PLL
if with_usb_pll: