fix compilation and use new cpu_csr_regions
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2
Makefile
2
Makefile
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@ -1,5 +1,5 @@
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MSCDIR = ../misoc
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CURDIR = ../sata_controller
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CURDIR = ../sata-controller
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PYTHON = python3
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TOOLCHAIN = vivado
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PLATFORM = kc705
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@ -140,7 +140,7 @@ class K7SATAPHYDatapath(Module):
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receive_align = Signal()
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self.comb += receive_align.eq(rx.source.stb &
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(rx.source.charisk == 0b0001) &
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(rx.source.data == primitives["ALIGN"])
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(rx.source.data == primitives["ALIGN"]))
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# user / ctrl mux
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self.comb += [
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@ -65,6 +65,8 @@ class UART2WB(Module):
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
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self._wb_masters = [self.uart2wb.wishbone]
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self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
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self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
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# CSR
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self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
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@ -79,6 +81,12 @@ class UART2WB(Module):
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raise FinalizeError
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self._wb_slaves.append((address_decoder, interface))
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def add_cpu_memory_region(self, name, origin, length):
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self.cpu_memory_regions.append((name, origin, length))
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def add_cpu_csr_region(self, name, origin, busword, obj):
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self.cpu_csr_regions.append((name, origin, busword, obj))
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def do_finalize(self):
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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@ -89,6 +97,10 @@ class UART2WB(Module):
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width)
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
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class SimDesign(UART2WB):
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default_platform = "kc705"
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@ -148,7 +160,7 @@ class TestDesign(UART2WB, AutoCSR):
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UART2WB.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform)
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self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True, default_speed="SATA2")
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self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True, default_speed="SATA1")
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self.comb += [
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self.sataphy_host.sink.stb.eq(1),
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self.sataphy_host.sink.data.eq(primitives["SYNC"]),
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