build: xilinx: Use F4PGA instead of deprecated Symbiflow
This commit is contained in:
Robert Szczepanski
parent
0941459061
commit
2c0f59536c
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@ -0,0 +1,159 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import math
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from migen.fhdl.structure import _Fragment
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from litex.build.generic_platform import *
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from litex.build.xilinx.vivado import _xdc_separator, _build_xdc
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from litex.build import tools
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try:
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from f4pga import Flow, make_flow_config
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from f4pga.common import set_verbosity_level
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from f4pga.cache import F4Cache
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from f4pga.flow_config import ProjectFlowConfig
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except ModuleNotFoundError as e:
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raise ModuleNotFoundError("Try getting/updating F4PGA tool (https://github.com/chipsalliance/f4pga/)") from e
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F4CACHEPATH = '.f4cache'
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# F4PGAToolchain -------------------------------------------------------------------------------
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# Formerly SymbiflowToolchain, Symbiflow has been renamed to F4PGA -----------------------------
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class F4PGAToolchain:
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attr_translate = {
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"keep": ("dont_touch", "true"),
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"no_retiming": ("dont_touch", "true"),
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"async_reg": ("async_reg", "true"),
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"mr_ff": ("mr_ff", "true"), # user-defined attribute
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"ars_ff1": ("ars_ff1", "true"), # user-defined attribute
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"ars_ff2": ("ars_ff2", "true"), # user-defined attribute
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"no_shreg_extract": None
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}
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def __init__(self):
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self.clocks = dict()
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self.false_paths = set()
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self._partname = None
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def _generate_prj_flow(self, platform, build_name):
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target = "bitstream"
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prj_flow_cfg_dict = {}
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prj_flow_cfg_dict["dependencies"] = {}
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prj_flow_cfg_dict["values"] = {}
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prj_flow_cfg_dict[self._partname] = {}
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deps_cfg = prj_flow_cfg_dict["dependencies"]
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deps_cfg["sources"] = [f for f,language,_ in platform.sources if language in ["verilog", "system_verilog"]]
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deps_cfg["xdc"] = f"{build_name}.xdc"
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deps_cfg["sdc"] = f"{build_name}.sdc"
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deps_cfg["build_dir"] = os.getcwd()
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deps_cfg["synth_log"] = f"{build_name}_synth.log"
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deps_cfg["pack_log"] = f"{build_name}_pack.log"
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deps_cfg["json"] = f"{build_name}.json"
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values_cfg = prj_flow_cfg_dict["values"]
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values_cfg["top"] = build_name
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values_cfg["part_name"] = self._partname
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prj_flow_cfg = ProjectFlowConfig("")
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prj_flow_cfg.flow_cfg = prj_flow_cfg_dict
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flow_cfg = make_flow_config(prj_flow_cfg, self._partname)
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flow = Flow(
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target=target,
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cfg=flow_cfg,
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f4cache=F4Cache(F4CACHEPATH)
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)
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print("\nProject status:")
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flow.print_resolved_dependencies(0)
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print("")
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return flow
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def _build_clock_constraints(self, platform):
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platform.add_platform_command(_xdc_separator("Clock constraints"))
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for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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platform.add_platform_command(
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"create_clock -period " + str(period) +
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" {clk}", clk=clk)
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def build(self, platform, fragment,
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build_dir = "build",
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build_name = "top",
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run = True,
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enable_xpm = False,
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**kwargs):
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# FIXME: prjxray-db doesn't have xc7a35ticsg324-1L and xc7a200t-sbg484-1
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# use closest replacement
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self._partname = {
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"xc7a35ticsg324-1L" : "xc7a35tcsg324-1",
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"xc7a200t-sbg484-1" : "xc7a200tsbg484-1",
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}.get(platform.device, platform.device)
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# Create build directory
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os.makedirs(build_dir, exist_ok=True)
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cwd = os.getcwd()
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os.chdir(build_dir)
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# Finalize design
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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# Generate timing constraints
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self._build_clock_constraints(platform)
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# Generate verilog
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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set_verbosity_level(2)
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# Generate design constraints
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tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
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flow = self._generate_prj_flow(
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platform = platform,
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build_name = build_name
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)
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if run:
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try:
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flow.execute()
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except Exception as e:
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print(e)
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flow.f4cache.save()
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os.chdir(cwd)
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return v_output.ns
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def add_period_constraint(self, platform, clk, period):
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clk.attr.add("keep")
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period = math.floor(period*1e3)/1e3 # round to lowest picosecond
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if clk in self.clocks:
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if period != self.clocks[clk]:
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raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
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.format(self.clocks[clk], period))
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self.clocks[clk] = period
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def add_false_path_constraint(self, platform, from_, to):
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# FIXME: false path constraints are currently not supported by the F4PGA toolchain
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return
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@ -26,9 +26,9 @@ class XilinxPlatform(GenericPlatform):
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elif toolchain == "vivado":
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from litex.build.xilinx import vivado
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self.toolchain = vivado.XilinxVivadoToolchain()
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elif toolchain == "symbiflow":
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from litex.build.xilinx import symbiflow
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self.toolchain = symbiflow.SymbiflowToolchain()
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elif toolchain == "symbiflow" or toolchain == "f4pga":
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from litex.build.xilinx import f4pga
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self.toolchain = f4pga.F4PGAToolchain()
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elif toolchain == "yosys+nextpnr":
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from litex.build.xilinx import yosys_nextpnr
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self.toolchain = yosys_nextpnr.YosysNextpnrToolchain()
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@ -1,265 +0,0 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import subprocess
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import sys
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import math
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from typing import NamedTuple, Union, List
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import re
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from shutil import which
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from migen.fhdl.structure import _Fragment, wrap, Constant
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from migen.fhdl.specials import Instance
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from litex.build.generic_platform import *
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from litex.build.xilinx.vivado import _xdc_separator, _format_xdc, _build_xdc
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from litex.build import tools
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from litex.build.xilinx import common
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def _unwrap(value):
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return value.value if isinstance(value, Constant) else value
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# Makefile -----------------------------------------------------------------------------------------
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class _MakefileGenerator:
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class Var(NamedTuple):
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name: str
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value: Union[str, List[str]] = ""
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class Rule(NamedTuple):
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target: str
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prerequisites: List[str] = []
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commands: List[str] = []
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phony: bool = False
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def __init__(self, ast):
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self.ast = ast
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def generate(self):
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makefile = []
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for entry in self.ast:
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if isinstance(entry, str):
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makefile.append(entry)
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elif isinstance(entry, self.Var):
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if not entry.value:
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makefile.append(f"{entry.name} :=")
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elif isinstance(entry.value, list):
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indent = " " * (len(entry.name) + len(" := "))
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line = f"{entry.name} := {entry.value[0]}"
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for value in entry.value[1:]:
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line += " \\"
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makefile.append(line)
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line = indent + value
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makefile.append(line)
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elif isinstance(entry.value, str):
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makefile.append(f"{entry.name} := {entry.value}")
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else:
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raise
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elif isinstance(entry, self.Rule):
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makefile.append("")
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if entry.phony:
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makefile.append(f".PHONY: {entry.target}")
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makefile.append(" ".join([f"{entry.target}:", *entry.prerequisites]))
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for cmd in entry.commands:
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makefile.append(f"\t{cmd}")
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return "\n".join(makefile)
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def _run_make():
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make_cmd = ["make", "-j1"]
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if which("symbiflow_synth") is None:
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msg = "Unable to find Symbiflow toolchain, please:\n"
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msg += "- Add Symbiflow toolchain to your $PATH."
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raise OSError(msg)
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if tools.subprocess_call_filtered(make_cmd, common.colors) != 0:
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raise OSError("Error occured during Symbiflow's script execution.")
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# SymbiflowToolchain -------------------------------------------------------------------------------
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class SymbiflowToolchain:
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attr_translate = {
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"keep": ("dont_touch", "true"),
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"no_retiming": ("dont_touch", "true"),
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"async_reg": ("async_reg", "true"),
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"mr_ff": ("mr_ff", "true"), # user-defined attribute
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"ars_ff1": ("ars_ff1", "true"), # user-defined attribute
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"ars_ff2": ("ars_ff2", "true"), # user-defined attribute
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"no_shreg_extract": None
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}
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def __init__(self):
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self.clocks = dict()
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self.false_paths = set()
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self.symbiflow_device = None
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self.bitstream_device = None
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self._partname = None
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def _check_properties(self, platform):
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if not self.symbiflow_device:
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try:
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self.symbiflow_device = {
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# FIXME: fine for now since only a few devices are supported, do more clever device re-mapping.
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"xc7a35tcpg236-1" : "xc7a50t_test",
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"xc7a35ticsg324-1L" : "xc7a50t_test",
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"xc7a100tcsg324-1" : "xc7a100t_test",
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"xc7a200t-sbg484-1" : "xc7a200t_test",
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"xc7z010clg400-1" : "xc7z010_test",
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"xc7z020clg400-1" : "xc7z020_test",
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}[platform.device]
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except KeyError:
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raise ValueError(f"symbiflow_device is not specified")
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if not self.bitstream_device:
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try:
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# bitstream_device points to a directory in prjxray database
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# available bitstream_devices: artix7, kintex7, zynq7
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self.bitstream_device = {
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"xc7a": "artix7", # xc7a35t, xc7a50t, xc7a100t, xc7a200t
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"xc7z": "zynq7", # xc7z010, xc7z020
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}[platform.device[:4]]
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except KeyError:
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raise ValueError(f"Unsupported device: {platform.device}")
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# FIXME: prjxray-db doesn't have xc7a35ticsg324-1L - use closest replacement
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self._partname = {
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"xc7a35ticsg324-1L" : "xc7a35tcsg324-1",
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"xc7a100tcsg324-1" : "xc7a100tcsg324-1",
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"xc7a200t-sbg484-1" : "xc7a200tsbg484-1",
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"xc7z010clg400-1" : "xc7z010clg400-1",
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"xc7z020clg400-1" : "xc7z020clg400-1",
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}.get(platform.device, platform.device)
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def _generate_makefile(self, platform, build_name):
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Var = _MakefileGenerator.Var
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Rule = _MakefileGenerator.Rule
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makefile = _MakefileGenerator([
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"# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n",
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Var("TOP", build_name),
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Var("PARTNAME", self._partname),
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Var("DEVICE", self.symbiflow_device),
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Var("BITSTREAM_DEVICE", self.bitstream_device),
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"",
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Var("VERILOG", [f for f,language,_ in platform.sources if language in ["verilog", "system_verilog"]]),
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Var("MEM_INIT", [f"{name}" for name in os.listdir() if name.endswith(".init")]),
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Var("SDC", f"{build_name}.sdc"),
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Var("XDC", f"{build_name}.xdc"),
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Var("ARTIFACTS", [
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"$(TOP).eblif", "$(TOP).frames", "$(TOP).ioplace", "$(TOP).net",
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"$(TOP).place", "$(TOP).route", "$(TOP)_synth.*",
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"*.bit", "*.fasm", "*.json", "*.log", "*.rpt",
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"constraints.place"
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]),
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Rule("all", ["$(TOP).bit"], phony=True),
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Rule("$(TOP).eblif", ["$(VERILOG)", "$(MEM_INIT)", "$(XDC)"], commands=[
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"symbiflow_synth -t $(TOP) -v $(VERILOG) -d $(BITSTREAM_DEVICE) -p $(PARTNAME) -x $(XDC) > /dev/null"
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]),
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#Rule("$(TOP).net", ["$(TOP).eblif", "$(SDC)"], commands=[ #SDC conflicts with make -j2 and seems not needed
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Rule("$(TOP).net", ["$(TOP).eblif"], commands=[
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"symbiflow_pack -e $(TOP).eblif -d $(DEVICE) -s $(SDC) > /dev/null"
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]),
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Rule("$(TOP).place", ["$(TOP).net"], commands=[
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"symbiflow_place -e $(TOP).eblif -d $(DEVICE) -n $(TOP).net -P $(PARTNAME) -s $(SDC) > /dev/null"
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]),
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Rule("$(TOP).route", ["$(TOP).place"], commands=[
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"symbiflow_route -e $(TOP).eblif -d $(DEVICE) -s $(SDC) > /dev/null"
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]),
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Rule("$(TOP).fasm", ["$(TOP).route"], commands=[
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"symbiflow_write_fasm -e $(TOP).eblif -d $(DEVICE) > /dev/null"
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]),
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Rule("$(TOP).bit", ["$(TOP).fasm"], commands=[
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"symbiflow_write_bitstream -d $(BITSTREAM_DEVICE) -f $(TOP).fasm -p $(PARTNAME) -b $(TOP).bit > /dev/null"
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]),
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Rule("clean", phony=True, commands=[
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"rm -f $(ARTIFACTS)"
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]),
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])
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tools.write_to_file("Makefile", makefile.generate())
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def _build_clock_constraints(self, platform):
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platform.add_platform_command(_xdc_separator("Clock constraints"))
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for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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platform.add_platform_command(
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"create_clock -period " + str(period) +
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" {clk}", clk=clk)
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def _fix_instance(self, instance):
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pass
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def build(self, platform, fragment,
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build_dir = "build",
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build_name = "top",
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run = True,
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enable_xpm = False,
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**kwargs):
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self._check_properties(platform)
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# Create build directory
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os.makedirs(build_dir, exist_ok=True)
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cwd = os.getcwd()
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os.chdir(build_dir)
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# Finalize design
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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# Symbiflow-specific fixes
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for instance in fragment.specials:
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if isinstance(instance, Instance):
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self._fix_instance(instance)
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# Generate timing constraints
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self._build_clock_constraints(platform)
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# Generate verilog
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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self._generate_makefile(
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platform = platform,
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build_name = build_name
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)
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# Generate design constraints
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tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
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if run:
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_run_make()
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os.chdir(cwd)
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return v_output.ns
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|
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def add_period_constraint(self, platform, clk, period):
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clk.attr.add("keep")
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period = math.floor(period*1e3)/1e3 # round to lowest picosecond
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if clk in self.clocks:
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if period != self.clocks[clk]:
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raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
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.format(self.clocks[clk], period))
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self.clocks[clk] = period
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def add_false_path_constraint(self, platform, from_, to):
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# FIXME: false path constraints are currently not supported by the symbiflow toolchain
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return
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def symbiflow_build_args(parser):
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pass
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def symbiflow_build_argdict(args):
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return dict()
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|
|
@ -100,14 +100,14 @@ class YosysNextpnrToolchain:
|
|||
def __init__(self):
|
||||
self.clocks = dict()
|
||||
self.false_paths = set()
|
||||
self.symbiflow_device = None
|
||||
self.f4pga_device = None
|
||||
self.bitstream_device = None
|
||||
self._partname = None
|
||||
|
||||
def _check_properties(self, platform):
|
||||
if not self.symbiflow_device:
|
||||
if not self.f4pga_device:
|
||||
try:
|
||||
self.symbiflow_device = {
|
||||
self.f4pga_device = {
|
||||
# FIXME: fine for now since only a few devices are supported, do more clever device re-mapping.
|
||||
"xc7a35ticsg324-1L" : "xc7a35t",
|
||||
"xc7a100tcsg324-1" : "xc7a35t",
|
||||
|
|
@ -115,7 +115,7 @@ class YosysNextpnrToolchain:
|
|||
"xc7z020clg400-1" : "xc7z020",
|
||||
}[platform.device]
|
||||
except KeyError:
|
||||
raise ValueError(f"symbiflow_device is not specified")
|
||||
raise ValueError(f"f4pga_device is not specified")
|
||||
if not self.bitstream_device:
|
||||
try:
|
||||
# bitstream_device points to a directory in prjxray database
|
||||
|
|
@ -143,7 +143,7 @@ class YosysNextpnrToolchain:
|
|||
"# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n",
|
||||
Var("TOP", build_name),
|
||||
Var("PARTNAME", self._partname),
|
||||
Var("DEVICE", self.symbiflow_device),
|
||||
Var("DEVICE", self.f4pga_device),
|
||||
Var("BITSTREAM_DEVICE", self.bitstream_device),
|
||||
"",
|
||||
Var("DB_DIR", "/usr/share/nextpnr/prjxray-db"), #FIXME: resolve path
|
||||
|
|
@ -253,12 +253,12 @@ class YosysNextpnrToolchain:
|
|||
self.clocks[clk] = period
|
||||
|
||||
def add_false_path_constraint(self, platform, from_, to):
|
||||
# FIXME: false path constraints are currently not supported by the symbiflow toolchain
|
||||
# FIXME: false path constraints are currently not supported by the F4PGA toolchain
|
||||
return
|
||||
|
||||
def symbiflow_build_args(parser):
|
||||
def f4pga_build_args(parser):
|
||||
pass
|
||||
|
||||
|
||||
def symbiflow_build_argdict(args):
|
||||
def f4pga_build_argdict(args):
|
||||
return dict()
|
||||
|
|
|
|||
Loading…
Reference in New Issue