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soc/cores/clock: make sure specific clkoutn_divide_range is only used as a fallback solution.

This commit is contained in:
Florent Kermarrec 2020-03-16 11:44:39 +01:00
parent 536ae0e619
commit 2c4b89639f
1 changed files with 14 additions and 10 deletions
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24
litex/soc/cores/clock.py
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@ -126,16 +126,20 @@ class XilinxClocking(Module, AutoCSR):
vco_freq <= vco_freq_max*(1 - self.vco_margin)): vco_freq <= vco_freq_max*(1 - self.vco_margin)):
for n, (clk, f, p, m) in sorted(self.clkouts.items()): for n, (clk, f, p, m) in sorted(self.clkouts.items()):
valid = False valid = False
d_range = self.clkout_divide_range d_ranges = [self.clkout_divide_range]
d_range = getattr(self, "clkout{}_divide_range".format(n), d_range) if getattr(self, "clkout{}_divide_range".format(n), None) is not None:
for d in clkdiv_range(*d_range): d_ranges += [getattr(self, "clkout{}_divide_range".format(n))]
clk_freq = vco_freq/d for d_range in d_ranges:
if abs(clk_freq - f) <= f*m: for d in clkdiv_range(*d_range):
config["clkout{}_freq".format(n)] = clk_freq clk_freq = vco_freq/d
config["clkout{}_divide".format(n)] = d if abs(clk_freq - f) <= f*m:
config["clkout{}_phase".format(n)] = p config["clkout{}_freq".format(n)] = clk_freq
valid = True config["clkout{}_divide".format(n)] = d
break config["clkout{}_phase".format(n)] = p
valid = True
break
if valid:
break
if not valid: if not valid:
all_valid = False all_valid = False
else: else: