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soc/cores/clock: make sure specific clkoutn_divide_range is only used as a fallback solution.

This commit is contained in:
Florent Kermarrec 2020-03-16 11:44:39 +01:00
parent 536ae0e619
commit 2c4b89639f
1 changed files with 14 additions and 10 deletions
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8
litex/soc/cores/clock.py
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@ -126,8 +126,10 @@ class XilinxClocking(Module, AutoCSR):
vco_freq <= vco_freq_max*(1 - self.vco_margin)):
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
valid = False
d_range = self.clkout_divide_range
d_range = getattr(self, "clkout{}_divide_range".format(n), d_range)
d_ranges = [self.clkout_divide_range]
if getattr(self, "clkout{}_divide_range".format(n), None) is not None:
d_ranges += [getattr(self, "clkout{}_divide_range".format(n))]
for d_range in d_ranges:
for d in clkdiv_range(*d_range):
clk_freq = vco_freq/d
if abs(clk_freq - f) <= f*m:
@ -136,6 +138,8 @@ class XilinxClocking(Module, AutoCSR):
config["clkout{}_phase".format(n)] = p
valid = True
break
if valid:
break
if not valid:
all_valid = False
else: