misoclib: better organization (create cores categories: cpu, mem, com, ...)

This commit is contained in:
Florent Kermarrec 2015-02-28 09:02:28 +01:00
parent 6b93849a08
commit 2c51adcd68
162 changed files with 246 additions and 237 deletions

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@ -8,7 +8,7 @@ from migen.fhdl import simplify
from misoclib.gensoc import cpuif
from misoclib.cpu import CPU
from misoclib.sdram.phy import initsequence
from misoclib.mem.sdram.phy import initsequence
from misoc_import import misoc_import

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@ -1,10 +1,10 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.mac import LiteEthMAC
from misoclib.liteeth.core.arp import LiteEthARP
from misoclib.liteeth.core.ip import LiteEthIP
from misoclib.liteeth.core.udp import LiteEthUDP
from misoclib.liteeth.core.icmp import LiteEthICMP
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.mac import LiteEthMAC
from misoclib.com.liteeth.core.arp import LiteEthARP
from misoclib.com.liteeth.core.ip import LiteEthIP
from misoclib.com.liteeth.core.udp import LiteEthUDP
from misoclib.com.liteeth.core.icmp import LiteEthICMP
class LiteEthIPCore(Module, AutoCSR):
def __init__(self, phy, mac_address, ip_address, clk_freq):

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@ -1,7 +1,7 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.liteeth.generic.packetizer import LiteEthPacketizer
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
_arp_table_layout = [
("reply", 1),

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@ -1,11 +1,11 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.generic.arbiter import Arbiter
from misoclib.liteeth.generic.dispatcher import Dispatcher
from misoclib.liteeth.core.etherbone.packet import *
from misoclib.liteeth.core.etherbone.probe import *
from misoclib.liteeth.core.etherbone.record import *
from misoclib.liteeth.core.etherbone.wishbone import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.generic.arbiter import Arbiter
from misoclib.com.liteeth.generic.dispatcher import Dispatcher
from misoclib.com.liteeth.core.etherbone.packet import *
from misoclib.com.liteeth.core.etherbone.probe import *
from misoclib.com.liteeth.core.etherbone.record import *
from misoclib.com.liteeth.core.etherbone.wishbone import *
class LiteEthEtherbone(Module):
def __init__(self, udp, udp_port):

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@ -1,7 +1,7 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.liteeth.generic.packetizer import LiteEthPacketizer
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
class LiteEthEtherbonePacketPacketizer(LiteEthPacketizer):
def __init__(self):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthEtherboneProbe(Module):
def __init__(self):

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@ -1,7 +1,7 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.liteeth.generic.packetizer import LiteEthPacketizer
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
class LiteEthEtherboneRecordPacketizer(LiteEthPacketizer):
def __init__(self):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from migen.bus import wishbone
class LiteEthEtherboneWishboneMaster(Module):

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@ -1,7 +1,7 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.liteeth.generic.packetizer import LiteEthPacketizer
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
class LiteEthICMPPacketizer(LiteEthPacketizer):
def __init__(self):

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@ -1,9 +1,9 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.core.ip.checksum import *
from misoclib.liteeth.core.ip.crossbar import *
from misoclib.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.liteeth.generic.packetizer import LiteEthPacketizer
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.core.ip.checksum import *
from misoclib.com.liteeth.core.ip.crossbar import *
from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
class LiteEthIPV4Packetizer(LiteEthPacketizer):
def __init__(self):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthIPV4Checksum(Module):
def __init__(self, words_per_clock_cycle=1, skip_checksum=False):

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@ -1,6 +1,6 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.generic.crossbar import LiteEthCrossbar
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.generic.crossbar import LiteEthCrossbar
class LiteEthIPV4MasterPort:
def __init__(self, dw):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthTTYTX(Module):
def __init__(self, ip_address, udp_port, fifo_depth=None):

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@ -1,8 +1,8 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.core.udp.crossbar import *
from misoclib.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.liteeth.generic.packetizer import LiteEthPacketizer
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.core.udp.crossbar import *
from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
class LiteEthUDPPacketizer(LiteEthPacketizer):
def __init__(self):

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@ -1,7 +1,7 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.liteeth.generic.crossbar import LiteEthCrossbar
from misoclib.com.liteeth.generic.crossbar import LiteEthCrossbar
class LiteEthUDPMasterPort:
def __init__(self, dw):

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Before

Width:  |  Height:  |  Size: 25 KiB

After

Width:  |  Height:  |  Size: 25 KiB

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Before

Width:  |  Height:  |  Size: 12 KiB

After

Width:  |  Height:  |  Size: 12 KiB

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@ -11,7 +11,7 @@ from mibuild import tools
from mibuild.xilinx_common import *
sys.path.append("../../../") # Temporary
from misoclib.liteeth.common import *
from misoclib.com.liteeth.common import *
def get_csr_csv(regions):
r = ""

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@ -14,10 +14,10 @@ from litescope.bridge.uart2wb import LiteScopeUART2WB
from litescope.frontend.la import LiteScopeLA
from litescope.core.port import LiteScopeTerm
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.phy.gmii import LiteEthPHYGMII
from misoclib.liteeth.core import LiteEthUDPIPCore
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
from misoclib.com.liteeth.core import LiteEthUDPIPCore
class _CRG(Module):
def __init__(self, platform):

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@ -2,11 +2,11 @@ from litescope.common import *
from litescope.frontend.la import LiteScopeLA
from litescope.core.port import LiteScopeTerm
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from targets.base import BaseSoC
from misoclib.liteeth.core.etherbone import LiteEthEtherbone
from misoclib.com.liteeth.core.etherbone import LiteEthEtherbone
class EtherboneSoC(BaseSoC):
default_platform = "kc705"

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@ -2,11 +2,11 @@ from litescope.common import *
from litescope.frontend.la import LiteScopeLA
from litescope.core.port import LiteScopeTerm
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from targets.base import BaseSoC
from misoclib.liteeth.core.tty import LiteEthTTY
from misoclib.com.liteeth.core.tty import LiteEthTTY
class TTYSoC(BaseSoC):
default_platform = "kc705"

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@ -2,8 +2,8 @@ from litescope.common import *
from litescope.frontend.la import LiteScopeLA
from litescope.core.port import LiteScopeTerm
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from targets.base import BaseSoC

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@ -1,5 +1,5 @@
import socket, time
from misoclib.liteeth.test.model.etherbone import *
from misoclib.com.liteeth.test.model.etherbone import *
SRAM_BASE = 0x02000000

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@ -1,4 +1,4 @@
from misoclib.liteeth.common import *
from misoclib.com.liteeth.common import *
# Generic classes
class Port:

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@ -1,9 +1,9 @@
from collections import OrderedDict
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.generic.arbiter import Arbiter
from misoclib.liteeth.generic.dispatcher import Dispatcher
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.generic.arbiter import Arbiter
from misoclib.com.liteeth.generic.dispatcher import Dispatcher
class LiteEthCrossbar(Module):
def __init__(self, master_port, dispatch_param):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
def _decode_header(h_dict, h_signal, obj):
r = []

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
def _encode_header(h_dict, h_signal, obj):
r = []

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@ -1,8 +1,8 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.mac.common import *
from misoclib.liteeth.mac.core import LiteEthMACCore
from misoclib.liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.mac.common import *
from misoclib.com.liteeth.mac.core import LiteEthMACCore
from misoclib.com.liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface
class LiteEthMAC(Module, AutoCSR):
def __init__(self, phy, dw, interface="crossbar", endianness="big",

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@ -1,8 +1,8 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.liteeth.generic.packetizer import LiteEthPacketizer
from misoclib.liteeth.generic.crossbar import LiteEthCrossbar
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
from misoclib.com.liteeth.generic.crossbar import LiteEthCrossbar
class LiteEthMACDepacketizer(LiteEthDepacketizer):
def __init__(self):

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@ -1,6 +1,6 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.mac.core import gap, preamble, crc, padding, last_be
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.mac.core import gap, preamble, crc, padding, last_be
class LiteEthMACCore(Module, AutoCSR):
def __init__(self, phy, dw, endianness="big", with_hw_preamble_crc=True):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthMACCRCEngine(Module):
"""Cyclic Redundancy Check Engine

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthMACGap(Module):
def __init__(self, dw, ack_on_gap=False):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthMACTXLastBE(Module):
def __init__(self, dw):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthMACPaddingInserter(Module):
def __init__(self, dw, packet_min_length):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthMACPreambleInserter(Module):
def __init__(self, dw):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from migen.bank.description import *
from migen.bank.eventmanager import *

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@ -1,6 +1,6 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.liteeth.mac.frontend import sram
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.mac.frontend import sram
from migen.bus import wishbone
from migen.fhdl.simplify import FullMemoryWE

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthPHYGMIITX(Module):
def __init__(self, pads):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthPHYLoopbackCRG(Module, AutoCSR):
def __init__(self):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthPHYMIITX(Module):
def __init__(self, pads):

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@ -1,5 +1,5 @@
from misoclib.liteeth.common import *
from misoclib.liteeth.generic import *
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
class LiteEthPHYSimCRG(Module, AutoCSR):
def __init__(self):

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