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interconnect/stream: add ClockDomainCrossing wrapper around AsyncFIFO.

This commit is contained in:
Florent Kermarrec 2020-07-03 14:39:31 +02:00
parent 23a95bea1d
commit 2c53f9b2ff
1 changed files with 17 additions and 0 deletions
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17
litex/soc/interconnect/stream.py
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@ -235,6 +235,23 @@ class AsyncFIFO(_FIFOWrapper):
layout = layout, layout = layout,
depth = depth) depth = depth)
# ClockDomainCrossing ------------------------------------------------------------------------------
class ClockDomainCrossing(Module):
def __init__(self, layout, cd_from="sys", cd_to="sys"):
self.sink = Endpoint(layout)
self.source = Endpoint(layout)
# # #
if cd_from == cd_to:
self.comb += self.sink.connect(self.source)
else:
cdc = AsyncFIFO(layout)
cdc = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(cdc)
self.submodules += cdc
self.comb += self.sink.connect(cdc.sink)
self.comb += cdc.source.connect(self.source)
# Mux/Demux ---------------------------------------------------------------------------------------- # Mux/Demux ----------------------------------------------------------------------------------------
class Multiplexer(Module): class Multiplexer(Module):