minicon: fix use of phy phases
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8418ccafdc
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2cd80990e4
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@ -47,8 +47,6 @@ class Minicon(Module):
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ROW = 2
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ROW = 2
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rdphase = phy_settings.rdphase
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rdphase = phy_settings.rdphase
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wrphase = phy_settings.wrphase
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wrphase = phy_settings.wrphase
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rdcmdphase = phy_settings.rdcmdphase
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wrcmdphase = phy_settings.wrcmdphase
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self.dfi = dfi = dfibus.Interface(geom_settings.mux_a,
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self.dfi = dfi = dfibus.Interface(geom_settings.mux_a,
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geom_settings.bank_a,
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geom_settings.bank_a,
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@ -137,9 +135,9 @@ class Minicon(Module):
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fsm.act("READ",
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fsm.act("READ",
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# We output Column bits at address pins so that A10 is 0
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# We output Column bits at address pins so that A10 is 0
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# to disable row Auto-Precharge
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# to disable row Auto-Precharge
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dfi.phases[rdcmdphase].ras_n.eq(1),
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dfi.phases[rdphase].ras_n.eq(1),
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dfi.phases[rdcmdphase].cas_n.eq(0),
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dfi.phases[rdphase].cas_n.eq(0),
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dfi.phases[rdcmdphase].we_n.eq(1),
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dfi.phases[rdphase].we_n.eq(1),
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dfi.phases[rdphase].rddata_en.eq(1),
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dfi.phases[rdphase].rddata_en.eq(1),
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addr_sel.eq(COLUMN),
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addr_sel.eq(COLUMN),
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NextState("READ-WAIT-ACK"),
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NextState("READ-WAIT-ACK"),
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@ -153,9 +151,9 @@ class Minicon(Module):
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)
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)
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)
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)
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fsm.act("WRITE",
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fsm.act("WRITE",
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dfi.phases[wrcmdphase].ras_n.eq(1),
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dfi.phases[wrphase].ras_n.eq(1),
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dfi.phases[wrcmdphase].cas_n.eq(0),
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dfi.phases[wrphase].cas_n.eq(0),
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dfi.phases[wrcmdphase].we_n.eq(0),
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dfi.phases[wrphase].we_n.eq(0),
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dfi.phases[wrphase].wrdata_en.eq(1),
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dfi.phases[wrphase].wrdata_en.eq(1),
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addr_sel.eq(COLUMN),
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addr_sel.eq(COLUMN),
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bus.ack.eq(1),
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bus.ack.eq(1),
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