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minicon: fix use of phy phases

This commit is contained in:
Sebastien Bourdeauducq 2014-11-27 22:13:17 +08:00
parent 8418ccafdc
commit 2cd80990e4
1 changed files with 9 additions and 11 deletions
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14
misoclib/sdram/minicon/__init__.py
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@ -47,8 +47,6 @@ class Minicon(Module):
ROW = 2
rdphase = phy_settings.rdphase
wrphase = phy_settings.wrphase
rdcmdphase = phy_settings.rdcmdphase
wrcmdphase = phy_settings.wrcmdphase
self.dfi = dfi = dfibus.Interface(geom_settings.mux_a,
geom_settings.bank_a,
@ -137,9 +135,9 @@ class Minicon(Module):
fsm.act("READ",
# We output Column bits at address pins so that A10 is 0
# to disable row Auto-Precharge
dfi.phases[rdcmdphase].ras_n.eq(1),
dfi.phases[rdcmdphase].cas_n.eq(0),
dfi.phases[rdcmdphase].we_n.eq(1),
dfi.phases[rdphase].ras_n.eq(1),
dfi.phases[rdphase].cas_n.eq(0),
dfi.phases[rdphase].we_n.eq(1),
dfi.phases[rdphase].rddata_en.eq(1),
addr_sel.eq(COLUMN),
NextState("READ-WAIT-ACK"),
@ -153,9 +151,9 @@ class Minicon(Module):
)
)
fsm.act("WRITE",
dfi.phases[wrcmdphase].ras_n.eq(1),
dfi.phases[wrcmdphase].cas_n.eq(0),
dfi.phases[wrcmdphase].we_n.eq(0),
dfi.phases[wrphase].ras_n.eq(1),
dfi.phases[wrphase].cas_n.eq(0),
dfi.phases[wrphase].we_n.eq(0),
dfi.phases[wrphase].wrdata_en.eq(1),
addr_sel.eq(COLUMN),
bus.ack.eq(1),