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soc/add_cpu: Make sure to reserve CPU's reserved interrupt when adding CPU.
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@ -1096,6 +1096,8 @@ class SoC(LiteXModule, SoCCoreCompat):
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colorer(name, color="underline"),
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colorer("adding", color="cyan")))
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self.irq.enable()
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if hasattr(self.cpu, "reserved_interrupts"):
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self.cpu.interrupts.update(self.cpu.reserved_interrupts)
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for name, loc in self.cpu.interrupts.items():
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self.irq.add(name, loc)
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self.add_config("CPU_HAS_INTERRUPT")
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