soc/add_cpu: Make sure to reserve CPU's reserved interrupt when adding CPU.

litex/soc/integration/soc.py

@@ -1096,6 +1096,8 @@ class SoC(LiteXModule, SoCCoreCompat):
                     colorer(name, color="underline"),
                     colorer("adding", color="cyan")))
                 self.irq.enable()
+                if hasattr(self.cpu, "reserved_interrupts"):
+                    self.cpu.interrupts.update(self.cpu.reserved_interrupts)
                 for name, loc in self.cpu.interrupts.items():
                     self.irq.add(name, loc)
                 self.add_config("CPU_HAS_INTERRUPT")