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Merge pull request #1838 from motec-research/etherbone

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Hybrid Etherbone simplification
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enjoy-digital 2023-11-13 08:48:29 +01:00 committed by GitHub
commit 2d9a268ff3
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2 changed files with 20 additions and 30 deletions
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21
litex/soc/integration/soc.py
View file

@ -1782,8 +1782,7 @@ class LiteXSoC(SoC):
buffer_depth = 16,
with_ip_broadcast = True,
with_timing_constraints = True,
interface = "crossbar",
endianness = "big"):
ethernet = False):
# Imports
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
@ -1802,10 +1801,10 @@ class LiteXSoC(SoC):
dw = data_width,
with_ip_broadcast = with_ip_broadcast,
with_sys_datapath = with_sys_datapath,
interface = interface,
endianness = endianness,
interface = "hybrid" if ethernet else "crossbar",
endianness = self.cpu.endianness if ethernet else "big",
)
if interface == "hybrid":
if ethernet:
ethcore.autocsr_exclude = {"mac"} # Exclude MAC here since added externally.
if not with_sys_datapath:
# Use PHY's eth_tx/eth_rx clock domains.
@ -1841,6 +1840,18 @@ class LiteXSoC(SoC):
else:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk)
if ethernet:
# Software Interface.
self.ethmac = ethmac = ethcore.mac
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)
self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)
# Add IRQs (if enabled).
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface.
# Add SPI Flash --------------------------------------------------------------------------------
def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=None, module=None, phy=None, rate="1:1", software_debug=False, **kwargs):
# Imports.

29
litex/tools/litex_sim.py
View file

@ -233,29 +233,16 @@ class SimSoC(SoCCore):
else:
raise ValueError("Unknown Ethernet PHY model:", ethernet_phy_model)
# Ethernet and Etherbone -------------------------------------------------------------------
if with_ethernet and with_etherbone:
# Etherbone.
# Etherbone with optional Ethernet ---------------------------------------------------------
if with_etherbone:
self.add_etherbone(
phy = self.ethphy,
ip_address = etherbone_ip_address,
mac_address = etherbone_mac_address,
data_width = 8,
interface = "hybrid",
endianness = self.cpu.endianness
ethernet = with_ethernet,
)
# Software Interface.
self.ethmac = ethmac = self.get_module("ethcore_etherbone").mac
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)
self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)
# Add IRQs (if enabled).
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Ethernet ---------------------------------------------------------------------------------
# Ethernet only ----------------------------------------------------------------------------
elif with_ethernet:
# Ethernet MAC
self.ethmac = ethmac = LiteEthMAC(
@ -272,14 +259,6 @@ class SimSoC(SoCCore):
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Etherbone --------------------------------------------------------------------------------
elif with_etherbone:
self.add_etherbone(
phy = self.ethphy,
ip_address = etherbone_ip_address,
mac_address = etherbone_mac_address
)
# I2C --------------------------------------------------------------------------------------
if with_i2c:
pads = platform.request("i2c", 0)