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soc_sdram: allow main_ram_size > 256MB (limitation no longer exists)

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Florent Kermarrec 2019-06-27 23:32:23 +02:00
parent b8d45af5c3
commit 2da59b29e2
1 changed files with 0 additions and 2 deletions
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litex/soc/integration/soc_sdram.py
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@ -66,11 +66,9 @@ class SoCSDRAM(SoCCore):
self.submodules.sdram = ControllerInjector( self.submodules.sdram = ControllerInjector(
phy, geom_settings, timing_settings, **kwargs) phy, geom_settings, timing_settings, **kwargs)
# TODO: modify mem_map to allow larger memories.
main_ram_size = 2**(geom_settings.bankbits + main_ram_size = 2**(geom_settings.bankbits +
geom_settings.rowbits + geom_settings.rowbits +
geom_settings.colbits)*phy.settings.databits//8 geom_settings.colbits)*phy.settings.databits//8
main_ram_size = min(main_ram_size, 256*1024*1024)
self.add_constant("L2_SIZE", self.l2_size) self.add_constant("L2_SIZE", self.l2_size)
# add a Wishbone interface to the DRAM # add a Wishbone interface to the DRAM