vexii l2 now support self flush. ex :
--l2-self-flush=40c00000,40DD4C00,1666666
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@ -49,6 +49,7 @@ class VexiiRiscv(CPU):
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litedram_width = 32
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litedram_width = 32
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l2_bytes = 0
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l2_bytes = 0
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l2_ways = 4
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l2_ways = 4
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l2_self_flush = None
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with_fpu = False
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with_fpu = False
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with_rvc = False
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with_rvc = False
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with_rvm = False
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with_rvm = False
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@ -57,6 +58,7 @@ class VexiiRiscv(CPU):
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jtag_instruction = False
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jtag_instruction = False
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vexii_args = ""
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vexii_args = ""
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# ABI.
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# ABI.
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@staticmethod
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@staticmethod
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def get_abi():
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def get_abi():
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@ -120,6 +122,8 @@ class VexiiRiscv(CPU):
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# cpu_group.add_argument("--with-rvc", action="store_true", help="Enable the Compress ISA extension.")
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# cpu_group.add_argument("--with-rvc", action="store_true", help="Enable the Compress ISA extension.")
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cpu_group.add_argument("--l2-bytes", default=0, help="VexiiRiscv L2 bytes, default 128 KB.")
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cpu_group.add_argument("--l2-bytes", default=0, help="VexiiRiscv L2 bytes, default 128 KB.")
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cpu_group.add_argument("--l2-ways", default=0, help="VexiiRiscv L2 ways, default 8.")
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cpu_group.add_argument("--l2-ways", default=0, help="VexiiRiscv L2 ways, default 8.")
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cpu_group.add_argument("--l2-self-flush", default=None, help="VexiiRiscv L2 ways will self flush on from,to,cycles")
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@ -130,7 +134,7 @@ class VexiiRiscv(CPU):
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vdir = get_data_mod("cpu", "vexiiriscv").data_location
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vdir = get_data_mod("cpu", "vexiiriscv").data_location
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ndir = os.path.join(vdir, "ext", "VexiiRiscv")
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ndir = os.path.join(vdir, "ext", "VexiiRiscv")
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "6912d4c5", args.update_repo)
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "0ec757d2", args.update_repo)
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if not args.cpu_variant:
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if not args.cpu_variant:
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args.cpu_variant = "standard"
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args.cpu_variant = "standard"
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@ -177,6 +181,8 @@ class VexiiRiscv(CPU):
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VexiiRiscv.l2_bytes = args.l2_bytes
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VexiiRiscv.l2_bytes = args.l2_bytes
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if args.l2_ways:
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if args.l2_ways:
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VexiiRiscv.l2_ways = args.l2_ways
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VexiiRiscv.l2_ways = args.l2_ways
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if args.l2_self_flush:
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VexiiRiscv.l2_self_flush = args.l2_self_flush
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def __init__(self, platform, variant):
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def __init__(self, platform, variant):
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@ -297,6 +303,7 @@ class VexiiRiscv(CPU):
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md5_hash.update(str(VexiiRiscv.cpu_count).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.cpu_count).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.l2_bytes).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.l2_bytes).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.l2_ways).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.l2_ways).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.l2_self_flush).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.jtag_tap).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.jtag_tap).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.jtag_instruction).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.jtag_instruction).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.with_dma).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.with_dma).encode('utf-8'))
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@ -322,6 +329,8 @@ class VexiiRiscv(CPU):
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gen_args.append(f"--cpu-count={VexiiRiscv.cpu_count}")
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gen_args.append(f"--cpu-count={VexiiRiscv.cpu_count}")
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gen_args.append(f"--l2-bytes={VexiiRiscv.l2_bytes}")
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gen_args.append(f"--l2-bytes={VexiiRiscv.l2_bytes}")
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gen_args.append(f"--l2-ways={VexiiRiscv.l2_ways}")
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gen_args.append(f"--l2-ways={VexiiRiscv.l2_ways}")
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if VexiiRiscv.l2_self_flush:
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gen_args.append(f"--l2-self-flush={VexiiRiscv.l2_self_flush}")
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gen_args.append(f"--litedram-width={VexiiRiscv.litedram_width}")
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gen_args.append(f"--litedram-width={VexiiRiscv.litedram_width}")
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# gen_args.append(f"--internal_bus_width={VexiiRiscv.internal_bus_width}")
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# gen_args.append(f"--internal_bus_width={VexiiRiscv.internal_bus_width}")
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for region in VexiiRiscv.memory_regions:
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for region in VexiiRiscv.memory_regions:
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