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- fix Spi2Csr mistakes

This commit is contained in:
Florent Kermarrec 2012-08-25 23:29:23 +02:00
parent b5a44f2e98
commit 2e54001fc1
2 changed files with 36 additions and 31 deletions
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20
sim/tb_spi2Csr.py
View File

@ -15,10 +15,12 @@ def get_bit(dat, bit):
return int(dat & (1<<bit) != 0)
def spi_transactions():
yield TWrite(0xA5A5,1)
yield TWrite(0x5A5A,2)
yield TWrite(0xA5A5,3)
yield TWrite(0x5A5A,4)
yield TWrite(0x8000,0x00)
yield TWrite(0x8001,0x01)
yield TWrite(0x8002,0x02)
yield TWrite(0x8003,0x03)
for i in range(100):
yield None
class SpiMaster(PureSimulable):
def __init__(self, spi, generator):
@ -50,17 +52,17 @@ class SpiMaster(PureSimulable):
s.wr(self.spi.spi_clk, 0)
# Mosi Addr
if self.transaction_cnt < a_w*2-1:
if self.transaction_cnt < a_w*2:
bit = a_w-1-int((self.transaction_cnt)/2)
data = get_bit(self.transaction.address, bit)
s.wr(self.spi.spi_mosi, data)
# Mosi Data
if self.transaction_cnt > a_w*2 and self.transaction_cnt < a_w*2+d_w*2-1:
elif self.transaction_cnt >= a_w*2 and self.transaction_cnt < a_w*2+d_w*2:
bit = d_w-1-int((self.transaction_cnt-a_w*2)/2)
data = get_bit(self.transaction.data,bit)
s.wr(self.spi.spi_mosi, data)
else:
s.wr(self.spi.spi_mosi, 0)
# Cs_n
if self.transaction_cnt < a_w*2+d_w*2:
@ -81,7 +83,7 @@ def main():
scratch_reg2 = RegisterField("scratch_reg3", 32, reset=0, access_dev=READ_ONLY)
scratch_reg3 = RegisterField("scratch_reg4", 32, reset=0, access_dev=READ_ONLY)
regs = [scratch_reg0, scratch_reg1, scratch_reg2, scratch_reg3]
bank0 = csrgen.Bank([scratch_reg0,],address=0x0000)
bank0 = csrgen.Bank(regs,address=0x0000)
# Spi2Csr
spi2csr0 = spi2Csr.Spi2Csr(16,8)

21
spi2Csr/__init__.py
View File

@ -12,10 +12,10 @@ class Spi2Csr :
self.csr = csr.Interface(self.d_width)
# Spi interface
self.spi_clk = Signal()
self.spi_cs_n = Signal()
self.spi_cs_n = Signal(reset=1)
self.spi_mosi = Signal()
self.spi_miso = Signal()
self.spi_int_n = Signal()
self.spi_int_n = Signal(reset=1)
def get_fragment(self):
comb = []
@ -82,14 +82,17 @@ class Spi2Csr :
last_b = Signal()
comb +=[
first_b.eq(spi_cnt[0:bits_for(self.d_width)] == 0),
last_b.eq(spi_cnt[0:bits_for(self.d_width)] == 2**self.d_width-1)
first_b.eq(spi_cnt[0:bits_for(self.d_width)-1] == 0),
last_b.eq(spi_cnt[0:bits_for(self.d_width)-1] == 2**(bits_for(self.d_width)-1)-1)
]
sync +=[
If(spi_cnt >= self.a_width & first_b,
If((spi_cnt >= (self.a_width + self.d_width)) & first_b,
spi_we.eq(spi_addr[self.a_width-1] & ~spi_we_re_done),
spi_re.eq(~spi_addr[self.a_width-1] & ~spi_we_re_done),
spi_we_re_done.eq(1)
).Elif((spi_cnt >= self.a_width) & first_b,
spi_re.eq(~spi_addr[self.a_width-1] & ~spi_we_re_done),
spi_we_re_done.eq(1)
).Else(
spi_we.eq(0),
spi_re.eq(0),
@ -104,15 +107,15 @@ class Spi2Csr :
).Elif(spi_clk_rising,
# addr
If(spi_cnt < self.a_width,
spi_addr.eq(spi_addr[0:self.a_width-1]&spi_mosi_dat)
).Elif(spi_cnt >= self.a_width+self.d_width & last_b,
spi_addr.eq(Cat(spi_mosi_dat,spi_addr[:self.a_width-1]))
).Elif((spi_cnt >= (self.a_width+self.d_width)) & last_b,
spi_addr.eq(spi_addr+1)
).Elif(spi_cnt >= self.a_width & last_b & spi_cnt[self.a_width-1] == 0,
).Elif((spi_cnt >= self.a_width) & last_b & (spi_cnt[self.a_width-1] == 0),
spi_addr.eq(spi_addr+1)
),
# dat
If(spi_cnt >= self.a_width,
spi_w_dat.eq(Cat(spi_w_dat[:self.d_width],spi_mosi_dat))
spi_w_dat.eq(Cat(spi_mosi_dat,spi_w_dat[:self.d_width-1]))
),
# spi_cnt