{Dep,P}acketizer: properly handle last_be wraparound
While the Depacketizer did correctly calculate a new last_be value for the data with the header removed, it may happen that the last_be overflows and thus relates to the current, non-delayed sink value. The same goes for the Packetizer, just inversed. This introduces logic in form of a simple FSM to handle these cases and properly output last_be on the last valid bus word. Co-authored-by: David Sawatzke <d-git@sawatzke.dev> Signed-off-by: Leon Schuermann <leon@is.currently.online>
This commit is contained in:
Leon Schuermann
parent
78c1751c47
commit
2e8586a090
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@ -185,15 +185,6 @@ class Packetizer(Module):
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if header_words != 1:
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self.sync += If(sr_shift, sr.eq(sr[data_width:]))
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# Last BE.
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last_be = Signal(data_width//8)
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last_be_d = Signal(data_width//8)
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if hasattr(sink, "last_be") and hasattr(source, "last_be"):
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rotate_by = header.length%bytes_per_clk
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x = [sink.last_be[(i + rotate_by)%bytes_per_clk] for i in range(bytes_per_clk)]
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self.comb += last_be.eq(Cat(*x))
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self.sync += last_be_d.eq(last_be)
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# FSM.
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm_from_idle = Signal()
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@ -231,11 +222,9 @@ class Packetizer(Module):
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)
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)
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)
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source_last_be = getattr(source, "last_be", Signal())
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fsm.act("ALIGNED-DATA-COPY",
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source.valid.eq(sink.valid),
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source.last.eq(sink.last),
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source_last_be.eq(last_be),
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source.data.eq(sink.data),
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If(source.valid & source.ready,
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sink.ready.eq(1),
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@ -250,7 +239,6 @@ class Packetizer(Module):
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fsm.act("UNALIGNED-DATA-COPY",
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source.valid.eq(sink.valid | sink_d.last),
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source.last.eq(sink_d.last),
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source_last_be.eq(last_be_d),
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If(fsm_from_idle,
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source.data[:max(header_leftover*8, 1)].eq(sr[min(header_offset_multiplier*data_width, len(sr)-1):])
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).Else(
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@ -266,6 +254,84 @@ class Packetizer(Module):
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)
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)
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# Last BE.
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if hasattr(sink, "last_be") and hasattr(source, "last_be"):
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# For an 8-bit data path, last_be really should be 1 when last is
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# asserted, other values do not make sense. However, legacy code
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# might not set last_be at all, and thus it will be set to 0. To
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# remain compatible with this code, this "corrects" last_be for
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# 8-bit paths by setting it to the value of last.
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if len(sink.last_be) == 1:
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sink_last_be = Signal.like(sink.last_be)
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self.comb += [ sink_last_be.eq(sink.last) ]
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else:
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sink_last_be = sink.last_be
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# last_be needs to be right-rotated by the number of bytes which
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# would be required to have a properly aligned header.
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right_rot_by = header_leftover
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# Calculate a rotated last_be
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new_last_be = Signal.like(sink_last_be)
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self.comb += [
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new_last_be.eq(Cat([
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sink_last_be[(i - right_rot_by) % bytes_per_clk]
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for i in range(bytes_per_clk)
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]))
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]
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# Conditionally delay the calculated last_be for one clock cycle, if
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# it now applies to the next bus word OR if the source is not ready.
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delayed_last_be = Signal.like(sink_last_be)
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# FSM used to conveniently assign combinational and synchronous
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# signals in the same context.
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self.submodules.last_be_fsm = last_be_fsm = FSM(reset_state="DEFAULT")
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# Whether the main FSM is in one of the DATA-COPY states. This is
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# important as we overwrite sink.ready below and need to have
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# different behavior depending on the Packetizer's state
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in_data_copy = Signal()
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self.comb += [
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in_data_copy.eq(self.fsm.ongoing("ALIGNED-DATA-COPY") | self.fsm.ongoing("UNALIGNED-DATA-COPY"))
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]
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self.last_be_fsm.act("DEFAULT",
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# Test whether our right-shift causes a wrap-around. In that
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# case apply the last value to the current bus word. Otherwise
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# delay it to the next.
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If(in_data_copy & sink.last & (sink_last_be > new_last_be),
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# Right shift did not wrap around, need to delay the
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# calculated last_be value and last by one cycle.
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source.last.eq(0),
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source.last_be.eq(0),
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If(source.ready & source.valid,
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NextValue(delayed_last_be, new_last_be),
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NextState("DELAYED"),
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),
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).Elif(in_data_copy,
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# Output the calculated last_be value on the current packet
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# already. For the next sink packet, ignore any last_be
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source.last.eq(sink.last),
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source.last_be.eq(new_last_be),
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),
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If(in_data_copy,
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sink.ready.eq(source.ready),
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).Elif(self.fsm.ongoing("IDLE"),
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sink.ready.eq(~sink.valid),
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)
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)
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self.last_be_fsm.act("DELAYED",
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# Output the delayed last and last_be signals
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source.last.eq(1),
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source.last_be.eq(delayed_last_be),
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sink.ready.eq(0),
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If(source.ready,
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NextState("DEFAULT"),
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),
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)
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# Error.
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if hasattr(sink, "error") and hasattr(source, "error"):
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self.comb += source.error.eq(sink.error)
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@ -373,9 +439,98 @@ class Depacketizer(Module):
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# Last BE.
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if hasattr(sink, "last_be") and hasattr(source, "last_be"):
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x = [sink.last_be[(i - (bytes_per_clk - header_leftover))%bytes_per_clk]
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for i in range(bytes_per_clk)]
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self.comb += source.last_be.eq(Cat(*x))
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# For an 8-bit data path, last_be really should be 1 when last is
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# asserted, other values do not make sense. However, legacy code
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# might not set last_be at all, and thus it will be set to 0. To
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# remain compatible with this code, this "corrects" last_be for
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# 8-bit paths by setting it to the value of last.
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if len(sink.last_be) == 1:
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sink_last_be = Signal.like(sink.last_be)
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self.comb += [ sink_last_be.eq(sink.last) ]
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else:
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sink_last_be = sink.last_be
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# last_be needs to be left-rotated by the number of bytes which
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# would be required to have a properly aligned header.
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left_rot_by = (bytes_per_clk - header_leftover) % bytes_per_clk
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# Calculate a rotated last_be
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new_last_be = Signal.like(sink_last_be)
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self.comb += [
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new_last_be.eq(Cat([
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sink_last_be[(i - left_rot_by) % bytes_per_clk]
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for i in range(bytes_per_clk)
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]))
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]
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# Conditionally delay the calculated last_be for one clock cycle, if
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# it now applies to the next bus word.
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delayed_last_be = Signal.like(sink_last_be)
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# FSM used to conveniently assign combinational and synchronous
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# signals in the same context.
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self.submodules.last_be_fsm = last_be_fsm = FSM(reset_state="DEFAULT")
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# Whether the main FSM is / was in one of the DATA-COPY states. This
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# is important as we must handle a special case when last is
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# asserted while the Depacketizer has just transitioned out of
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# writing the header, which we can then detect by checking
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# (~was_in_copy & is_in_copy).
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is_in_copy = Signal()
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was_in_copy = Signal()
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self.comb += [
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is_in_copy.eq(
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self.fsm.ongoing("ALIGNED-DATA-COPY") | self.fsm.ongoing("UNALIGNED-DATA-COPY")
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)
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]
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self.sync += [
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was_in_copy.eq(is_in_copy)
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]
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self.last_be_fsm.act("DEFAULT",
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# Test whether our left-shift has caused an wrap-around, in that
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# case delay last and last_be and apply to the next bus word.
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If(sink.valid & sink.last & (sink_last_be > new_last_be),
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# last_be did wrap around. Need to delay the calculated
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# last_be value and last by one cycle.
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source.last.eq(0),
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source.last_be.eq(0),
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# Normally just wait until a source bus transaction occurred
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# (ready + valid) until the delayed last_be can be
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# output. However, if the first word is also the last, this
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# will mean that the source isn't valid currently as the
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# header is still being sent. Thus, if sink.valid and
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# sink.last and we've just transitioned into the data copy
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# phase, we can immediately jump into the DELAYED state (as
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# the very first bus word containing proper data is also the
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# last one, and we've just transitioned to putting that on
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# the bus).
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If((source.ready & source.valid) | (~was_in_copy & is_in_copy),
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NextValue(delayed_last_be, new_last_be),
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NextState("DELAYED"),
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),
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).Elif(sink.last,
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# Simply forward the calculated last_be value.
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source.last.eq(1),
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source.last_be.eq(new_last_be),
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),
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If(self.fsm.ongoing("ALIGNED-DATA-COPY") \
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| (self.fsm.ongoing("UNALIGNED-DATA-COPY") & ~fsm_from_idle),
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sink.ready.eq(source.ready),
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).Else(
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sink.ready.eq(1),
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),
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)
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self.last_be_fsm.act("DELAYED",
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# Output the delayed last and last_be signals
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source.last.eq(1),
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source.last_be.eq(delayed_last_be),
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sink.ready.eq(0),
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If(source.ready & source.valid,
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NextState("DEFAULT"),
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),
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)
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# PacketFIFO ---------------------------------------------------------------------------------------
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