doc: fix warnings during doc build
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doc/api.rst
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doc/api.rst
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@ -2,42 +2,42 @@ migen API Documentation
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=======================
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:mod:`fhdl.structure` Module
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------------------------------
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----------------------------
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.. automodule:: migen.fhdl.structure
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:members:
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:show-inheritance:
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:mod:`fhdl.bitcontainer` Module
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------------------------------
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-------------------------------
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.. automodule:: migen.fhdl.bitcontainer
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:members:
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:show-inheritance:
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:mod:`genlib.fifo` Module
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------------------------------
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-------------------------
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.. automodule:: migen.genlib.fifo
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:members:
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:show-inheritance:
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:mod:`genlib.coding` Module
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------------------------------
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---------------------------
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.. automodule:: migen.genlib.coding
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:members:
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:show-inheritance:
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:mod:`genlib.cordic` Module
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------------------------------
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---------------------------
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.. automodule:: migen.genlib.cordic
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:members:
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:show-inheritance:
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:mod:`genlib.sort` Module
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------------------------------
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-------------------------
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.. automodule:: migen.genlib.sort
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:members:
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102
doc/fhdl.rst
102
doc/fhdl.rst
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@ -260,57 +260,57 @@ Summary of special attributes
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.. table:: Summary of special attributes
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+--------------------------------------------+--------------------------------------------------------------+
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| Syntax | Action |
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+============================================+==============================================================+
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| self.comb += stmt | Add combinatorial statement to current module. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.comb += stmtA, stmtB | Add combinatorial statements A and B to current module. |
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| | |
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| self.comb += [stmtA, stmtB] | |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.sync += stmt | Add synchronous statement to current module, in default |
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| | clock domain sys. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.sync.foo += stmt | Add synchronous statement to current module, in clock domain |
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| | foo. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.sync.foo += stmtA, stmtB | Add synchronous statements A and B to current module, in |
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| | clock domain foo. |
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| self.sync.foo += [stmtA, stmtB] | |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.submodules += mod | Add anonymous submodule to current module. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.submodules += modA, modB | Add anonymous submodules A and B to current module. |
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| | |
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| self.submodules += [modA, modB] | |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.submodules.bar = mod | Add submodule named bar to current module. The submodule can |
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| | then be accessed using self.bar. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.specials += spe | Add anonymous special to current module. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.specials += speA, speB | Add anonymous specials A and B to current module. |
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| | |
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| self.specials += [speA, speB] | |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.specials.bar = spe | Add special named bar to current module. The special can |
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| | then be accessed using self.bar. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.clock_domains += cd | Add clock domain to current module. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.clock_domains += cdA, cdB | Add clock domains A and B to current module. |
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| | |
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| self.clock_domains += [cdA, cdB] | |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.clock_domains.pix = ClockDomain() | Create and add clock domain pix to current module. The clock |
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| | domain name is pix in all cases. It can be accessed using |
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| self.clock_domains._pix = ClockDomain() | self.pix, self._pix, self.cd_pix and self._cd_pix, |
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| | respectively. |
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| self.clock_domains.cd_pix = ClockDomain() | |
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| | |
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| self.clock_domains._cd_pix = ClockDomain() | |
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+--------------------------------------------+--------------------------------------------------------------+
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+--------------------------------------------+--------------------------------------------------------------+
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| Syntax | Action |
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+============================================+==============================================================+
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| self.comb += stmt | Add combinatorial statement to current module. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.comb += stmtA, stmtB | Add combinatorial statements A and B to current module. |
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| | |
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| self.comb += [stmtA, stmtB] | |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.sync += stmt | Add synchronous statement to current module, in default |
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| | clock domain sys. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.sync.foo += stmt | Add synchronous statement to current module, in clock domain |
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| | foo. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.sync.foo += stmtA, stmtB | Add synchronous statements A and B to current module, in |
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| | clock domain foo. |
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| self.sync.foo += [stmtA, stmtB] | |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.submodules += mod | Add anonymous submodule to current module. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.submodules += modA, modB | Add anonymous submodules A and B to current module. |
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| | |
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| self.submodules += [modA, modB] | |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.submodules.bar = mod | Add submodule named bar to current module. The submodule can |
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| | then be accessed using self.bar. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.specials += spe | Add anonymous special to current module. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.specials += speA, speB | Add anonymous specials A and B to current module. |
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| | |
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| self.specials += [speA, speB] | |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.specials.bar = spe | Add special named bar to current module. The special can |
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| | then be accessed using self.bar. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.clock_domains += cd | Add clock domain to current module. |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.clock_domains += cdA, cdB | Add clock domains A and B to current module. |
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| | |
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| self.clock_domains += [cdA, cdB] | |
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+--------------------------------------------+--------------------------------------------------------------+
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| self.clock_domains.pix = ClockDomain() | Create and add clock domain pix to current module. The clock |
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| | domain name is pix in all cases. It can be accessed using |
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| self.clock_domains._pix = ClockDomain() | self.pix, self._pix, self.cd_pix and self._cd_pix, |
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| | respectively. |
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| self.clock_domains.cd_pix = ClockDomain() | |
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| | |
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| self.clock_domains._cd_pix = ClockDomain() | |
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+--------------------------------------------+--------------------------------------------------------------+
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Clock domain management
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=======================
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