Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2013-03-15 19:50:24 +01:00
parent e2d156ef64
commit 2f522bdd9f
1 changed files with 7 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
migen/genlib/cdc.py
View file

@ -30,6 +30,13 @@ class MultiReg(Special):
self.odomain = odomain
self.n = n
def rename_clock_domain(self, old, new):
if self.odomain == old:
self.odomain = new
def get_clock_domains(self):
return {self.odomain}
def list_ios(self, ins, outs, inouts):
r = set()
if ins: